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US 9,178,496 B2Granted
Low leakage retention register tray
AssigneeQUALCOMM Incorporated
InventorsRamaprasath Vilangudipitchai, Prayag Bhanubhai Patel
Life of this patent
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Abstract
A particular method includes receiving a retention signal. In response to receiving the retention signal, the method includes retaining state information in a non-volatile stage of a retention register and reducing power to a volatile stage of the retention register. The non-volatile stage may be powered by an external voltage source. The volatile stage may be powered by an internal voltage source.
Claims9
A circuit comprising:
- a first retention register that includes a first non-volatile region and a first volatile region;
- and
- a second retention register that includes a second non-volatile region and a second volatile region, wherein the first retention register is coupled to the second retention register, and the second volatile region comprises:
- a multiplexer configured to select a shift data signal from the first retention register or an input data signal according to a shift signal;
- and
- a volatile retention stage configured to latch the selected one of the shift data signal and the input data signal according to a clock signal;
- wherein the first non-volatile region and the second non-volatile region are located in a first n-type well (n-well) that is connected to an external voltage source, and wherein the first volatile region and the second volatile region are located in a second n-well that is connected to an internal voltage source.
4 more elements
A circuit comprising:
- a first retention register that includes a first non-volatile region and a first volatile region;
- a second retention register that includes a second non-volatile region and a second volatile region, wherein the first retention register and the second retention register form a retention register tray;
- and
- a clock gating circuit configured to supply a clock signal to the first retention register and to supply the clock signal to the second retention register, wherein the first non-volatile region, the second non-volatile region and the clock gating circuit are located in a first n-type well (n-well) that is connected to an external voltage source, and wherein the first volatile region and the second volatile region are located in a second n-well that is connected to an internal voltage source.
1 more element
A method comprising:
- in response to receiving a retention signal:
- retaining state information in a non-volatile stage of a retention register;
- and
- reducing power to a volatile stage of the retention register, wherein the non-volatile stage is powered by an external voltage source, the volatile stage is powered by an internal voltage source, and the non-volatile stage comprises a stack of transistors;
- and
- in response to receiving a reset signal, reverse biasing one or more transistors in the stack of transistors to reduce leakage current.
3 more elements
An apparatus comprising:
- means for retaining state information in a non-volatile stage of a retention register in response to receiving a retention signal;
- means for reducing power to a volatile stage of the retention register in response to receiving the retention signal, wherein the non-volatile stage is powered by an external voltage source, the volatile stage is powered by an internal voltage source, and the non-volatile stage comprises a stack of transistors;
- and
- means for reverse biasing one or more transistors in the stack of transistors to reduce leakage current in response to receiving a reset signal.
1 more element
Dependencies are inferred from the claim text.