Square root raised cosine symmetric filter for mobile telecommunications
AssigneeIntel Corporation
InventorsTinku Acharya, George J. Miao
Life of this patent
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Abstract
A symmetric discrete-time square-root-raised-cosine filter may be utilized to process a serial input signal and to produce an output square in each clock cycle. The filter may be adapted to decrease the computational complexity of the resulting calculations, making the filter amenable to use in power sensitive applications and in those situations where the available processor's performance is relatively limited.
Claims18
A discrete-time square-root-raised-cosine filter comprising a symmetric finite impulse response filter to generate, during transition from a passband to a stopband, an output ripple signal having a magnitude at a frequency of one half of the chip rate of about 3 decibels less than a normalized gain;
- a plurality of processing units;
- and
- wherein said symmetric finite impulse response filter to limit tolerable gain approximation error in said passband and said stopband, said tolerable gain approximation error is to be within unity of a first gain magnitude during said passband.
A wide band code division multiple access transceiver comprising:
- an analog processing section;
- a digital processing section coupled to said analog processing section, said digital processing section including an odd, symmetric, finite impulse response filter, said filter including a plurality of processing units implementing a systolic architecture, and said filter constructed to generate, during transition from a passband to a stopband, an output ripple signal having a magnitude at a frequency of one half of the chip rate of about 3 decibels less than a normalized gain in response to each input clock signal;
- wherein the edge of the stop band frequency of said filter having ninety-nine percent of half of the occupied bandwidth;
- wherein the filter coefficients are not equal to zero for even integer sample numbers;
- and
- wherein the self-convolution of the filter has coefficients approximately equal to zero for even integer sample numbers.
A method of implementing a code division multiple access receiver comprising:
- receiving a code division multiple access signal;
- generating, during transition from a passband to a stopband, an output ripple signal having a magnitude at a frequency of one-half of the chip rate of about three decibels less than a normalized gain;
- processing said received signal through a first filter having a systolic architecture;
- and
- causing the self convolution of said filter to have coefficients that are approximately equal to zero for even integer sample numbers.
Dependencies are inferred from the claim text.