Battery charger with segmented power path switch

#1. Field of the Invention

#The present invention relates generally to battery charger circuitry and in particular to circuitry which includes a power path switch and associated control circuitry.

#2. Description of Related Art

#FIG. 1 is a simplified circuit diagram of a prior art battery charger utilizing a DC-DC switching converter.

#FIG. 2 is a timing diagram of a battery charging sequence further illustrating operation of the FIG. 1 battery charger.

#FIG. 3 is a circuit diagram of a battery charger in accordance with one embodiment of the present invention.

#Referring again to the drawings, FIG. 3 shows one embodiment of the present invention. The battery charger includes a buck switching regulator which includes a high side P type transistor 14 and low side N type transistor 16, having a common node connected to one side of inductor 18. An external power source provides an input voltage VBUS to the switching regulator at the source of transistor 14. A controller 30 is provided for driving a P MOS driver 32 and an N MOS drive 34. Controller 30 operates to provide a switching signal to the drivers 32 and 34 in response to an error voltage applied to one of the inputs of the controller 36. The other inputs to controller 36 include a clock signal from clock source 38 and a saw tooth signal 39 used by pulse width modulation circuitry located in controller 36 to provide voltage regulation by changing the duty cycle of the transistor switches 14 and 16.

#The other end of inductor 18 is connected to a filter capacitor 20 and to an output voltage node that provides output voltage VDD. Voltage VDD functions both as a battery charging source and a power source for a system bus, with the system bus being powered by the battery except when the battery is in a discharged state or absent.

#The error voltage on line 41 coupled to controller 36 is applied to one input of a comparator (not depicted) within the controller, with the other input being the saw tooth signal 39 so as provide the pulse width modulation function. Various different error amplifiers are used to generate the error voltage. Each error amplifier includes a source-follower output stage which includes a P type transistor (not depicted) having a drain electrode connected to ground and an open source electrode output connected to common line 41. A current source 37 is connected between line 41 and supply voltage VDD. Although each error amplifier remains active during the various modes of charger operation, only the error amplifier with the lowest value error voltage actually controls the magnitude of the error voltage on line 41 and thus controls the loop. In other words, the error amplifier with smallest error voltage overrides the outputs of the other error amplifiers having higher error voltages. This is an analog analogy to a digital wired OR circuit.