Magnetoresistive random access memory cell and fabricating the same

#In integrated circuit (IC) devices, magnetroresistive random access memory (MRAM) is an emerging technology for next generation embedded memory devices. MRAM is a memory device including an array of MRAM cells, each of which stores a bit of data using resistance values, rather than electronic charge. Each MRAM cell includes a magnetic tunnel junction (“MTJ”) cell, the resistance of which can be adjusted to represent logic “0” or logic “1”. The MTJ cell includes an anti-ferromagnetic (“AFM”) pinning layer, a ferromagnetic fixed, or pinned, layer, a thin tunneling layer, and a ferromagnetic free layer. The resistance of the MTJ cell may be adjusted by changing the direction of the magnetic moment of the ferromagnetic free layer with respect to that of the fixed magnetic layer. In particular, when the magnetic moment of the ferromagnetic free layer is parallel to that of the ferromagnetic fixed layer, the resistance of the MTJ cell is low, corresponding to a logic 0, whereas when the magnetic moment of the ferromagnetic free layer is anti-parallel to that of the ferromagnetic fixed layer, the resistance of the MTJ cell is high, corresponding to a logic 1. The MTJ cell is coupled between top and bottom electrodes and an electric current flowing through the MTJ cell from one electrode to the other may be detected to determine the resistance, and therefore the logic state. However, various damages to the MTJ cell, including damage to the free ferromagnetic layer and the tunneling layer during an etching in the fabrication, result in poor performance of the MTJ cell.

#Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

#FIG. 1 is a flowchart of an example method for fabricating a semiconductor memory device constructed according to various aspects of the present disclosure.

#FIGS. 2 and 3 are cross-sectional views of an example semiconductor memory device at fabrication stages constructed according to the method of FIG. 1.

#It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Moreover, the performance of a first process before a second process in the description that follows may include embodiments in which the second process is performed immediately after the first process, and may also include embodiments in which additional processes may be performed between the first and second processes. Various features may be arbitrarily drawn in different scales for the sake of simplicity and clarity. Furthermore, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact.

#Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

#FIG. 1 is a flowchart of a method 100 of making a MRAM device constructed according to aspects of the present disclosure. For the sake of example, the method 100 will be described with reference to a MRAM device 200 shown in FIG. 2. The MRAM device 200 is a portion of one non-volatile random access memory (RAM), such as a spin torque transfer magnetroresistive random access memory (STT-MRAM). In an embodiment, the MRAM device 200 includes a stack of material layers designed and configured to function as a magnetic tunnel junction (MTJ).