US 9,178,070 B2Granted

Semiconductor structure and method for manufacturing the same

AssigneeInstitute of Microelectronics, Chinese Academy of Sciences

InventorsHuilong Zhu, Qingqing Liang, Zhijiong Luo, Haizhou Yin

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Abstract

The present application discloses a semiconductor structure and a method for manufacturing the same. A semiconductor structure according to the present invention can adjust the threshold voltage by capacitive coupling between a backgate region either and a source region or a drain region with a common contact, i.e. a source contact or a drain contact, which leads to a simple manufacturing process, a higher integration level, and a lower manufacture cost. Moreover, the asymmetric design of the backgate structure, together with the doping of the backgate region which can be varied as required in an actual device design, can further enhance the effects of adjusting the threshold voltage and improve the performances of the device.

Claims12

Dependent claims

A semiconductor structure, comprising

an SOI structure, comprising an SOI layer, a first buried insulating layer, an additional SOI layer, a second buried insulating layer, and a base substrate in this order from top to bottom;
a shallow trench isolation embedded in the SOI structure and above the second buried insulation layer;
a gate on the SOI structure;
a source region and a drain region on opposite sides of the gate;
and
a source contact and a drain contact,
wherein the additional SOI layer comprises an asymmetric backgate region and a laterally adjacent dielectric portion which are sandwiched between the first buried insulation layer and the second buried insulating layer, and the asymmetric backgate region is formed by doping a portion of the additional SOI layer that is formed in-situ within the additional SOI layer;
wherein the backgate region comprises a portion of the additional SOI layer below either the source region or the drain region and a portion of the additional SOI layer below the gate;
and
wherein the other one of the source region or the drain region is over the adjacent dielectric portion.

7 more elements

A method for manufacturing a semiconductor structure, comprising:

providing an SOI structure which comprises an SOI layer, a first buried insulating layer, an additional SOI layer, a second buried insulating layer, and a base substrate in this order from top to bottom;
forming a shallow trench isolation embedded in the SOI structure and above the second buried insulation layer;
forming an asymmetric backgate region by reducing the electrical resistance of a portion of the additional SOI layer;
forming a gate on the SOI structure, and forming a source region and a drain region on opposite sides of the gate;
wherein the additional SOI layer comprises the asymmetric backgate region and a laterally adjacent dielectric portion which are sandwiched between the first buried insulation layer and the second buried insulating layer, the asymmetric backgate region being formed by doping a portion of the additional SOI layer that is formed in-situ within the additional SOI layer, a portion of the additional SOI layer being below either the source region or the drain region and a portion of the additional SOI layer below the gate, and wherein the other one of the source region or the drain region is over the adjacent dielectric portion;
and
forming a source contact and a drain contact.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/138,053Filed 4 Mar 2011
Priority: CN 2010 1 057435730 Nov 2010
Published: US 2012/0132990 A131 May 2012
Granted: 3 Nov 2015
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10P 30/204
Characterised by the semiconductor materials: into Group IV semiconductors
H10D 30/0323
Comprising silicon, e.g. amorphous silicon or polysilicon: comprising monocrystalline silicon
H10D 30/6706
Having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device: for…
H10D 30/673
Characterised by the electrodes: characterised by the shapes, relative sizes or dispositions of the gate electrodes