MOS transistor, fabrication method thereof, and SRAM memory cell circuit

A method of forming a transistor comprising:

• providing a semiconductor substrate;
• forming a gate structure on the semiconductor substrate;
• forming a tensile stressing layer in the semiconductor substrate on one side of the gate structure as one of a source region and a drain region;
• and
• forming a compressive stressing layer in the semiconductor substrate on an other side of the gate structure as an other of the source region and the drain region to provide the transistor with a channel region,
• wherein the channel region has a first end contacting only the tensile stressing layer and a second end contacting only the compress stressing layer to generate an asymmetric stress that gradually varies from a tensile stress to a compress stress in the channel region, and the tensile stressing layer and the compress stressing layer are symmetrically configured on both sides of the gate structure, and wherein the first end contacting the tensile stressing layer provides a largest saturation mobility of electrons in the channel region and the second end contacting the compress stressing layer provides a largest saturation mobility of holes in the channel region, and in a middle point of a width of the channel region, each of the compressive stress and the tensile stress becomes zero.

An SRAM memory cell circuit comprising:

• a first transfer transistor including a gate electrically connected to a word line, a source electrically connecting to a first storage node, and a drain electrically connecting to a first bit line;
• a second transfer transistor including a gate electrically connected to the word line, a source electrically connecting to a second storage node, and a drain electrically connecting to a second bit line, wherein each of the first transfer transistor and the second transfer transistor includes:
• a channel region between the source and the drain, wherein:
• one of the source and the drain includes a tensile stressing layer and an other of the source and the drain includes a compressive stressing layer,
• the channel region has a first end contacting only the tensile stressing layer and a second end contacting only the compress stressing layer to generate an asymmetric stress that gradually varies from a tensile stress to a compressive stress in the channel region from the first end to the second end of the channel region to allow both a read margin and a write margin of the SRAM memory cell to be increased at a same time, wherein the tensile stressing layer and the compress stressing layer are symmetrically configured on both sides of the gate structure, and in a middle point of a width of the channel region, each of the compressive stress and the tensile stress becomes zero.