Method for fabricating MOSFET on silicon-on-insulator with internal body contact

A method for fabricating a semiconductor device, the method comprising:

• providing a semiconductor-on-insulator substrate including a buried insulator layer and an overlying semiconductor layer, the semiconductor layer being doped with a dopant of a first conductivity type;
• forming a gate structure on the semiconductor layer, the gate structure comprising a gate dielectric layer located on the semiconductor layer and a gate conductor layer located on the gate dielectric layer, the gate structure including a first gate portion extending in a first direction, and a plurality of second gate portions that each extend from the first gate portion in a second direction, which is perpendicular to the first direction;
• forming a gate spacer abutting sidewalls of the gate conductor layer and the gate dielectric layer of one of the second gate portions of the gate structure;
• forming a source extension region and a drain extension region in the semiconductor layer, the source extension region and the drain extension region extending under the gate dielectric layer and the gate conductor layer, the source extension region and the drain extension region contacting the gate dielectric layer of the one second gate portion, the source extension region and the drain extension region being doped with a dopant of a second conductivity type, which is opposite the first conductivity type;
• after forming the source extension region and the drain extension region, forming a mask comprising a first open region, a second open region, and a blocking region, the first open region exposing a first portion of the semiconductor layer, the first portion of the semiconductor layer being located at an end of the semiconductor layer that is closest to the first gate portion of the gate structure, the second open region exposing second portion of the semiconductor layer comprising the entire drain extension region, the blocking region being formed over and blocking a third portion of the semiconductor layer, the third portion of the semiconductor layer being located at an end of the semiconductor layer that is furthest from the first gate portion of the gate structure;
• after forming the mask, forming a deep drain region in the semiconductor layer on one side of the one second gate portion, the deep drain region contacting the drain extension region and abutting the buried insulator layer;
• after forming the mask, forming a deep source region in the first portion of the semiconductor layer on an opposite side of the one second gate portion, the deep source region contacting the source extension region and abutting the buried insulator layer, the mask preventing a deep source region from being formed within the third portion of the semiconductor layer, the deep drain region and the deep source region being doped with a dopant of the second conductivity type;
• after forming the deep drain region and the deep source region, removing the mask;
• forming a drain metal-semiconductor alloy contact on an upper portion of the deep drain region and abutting the drain extension region;
• forming a source metal-semiconductor alloy contact abutting the source extension region;
• and
• wherein a body region is located in the semiconductor layer,
• a first portion of the source metal-semiconductor alloy contact is located above and directly contacts the deep source region,
• a first portion of the body region is below and directly contacts the gate dielectric layer of the one second gate portion,
• a second portion of the body region is below and directly contacts a second portion of the source metal-semiconductor alloy contact formed in the third portion of the semiconductor layer to form an internal body contact,
• the second portion of the source metal-semiconductor alloy contact is located at an end of the source metal-semiconductor alloy contact that is furthest from the first gate portion of the gate structure,
• the gate spacer directly contacts the second portion of the source metal-semiconductor alloy contact that is located above and directly contacts the second portion of the body region of the semiconductor layer,
• a vertical sidewall of the source extension region directly contacts both a vertical sidewall of the second portion of the source metal-semiconductor alloy contact and a vertical sidewall of the first portion of the source metal-semiconductor alloy contact, and a doping concentration of the first portion of the body region of the semiconductor layer is the same as a doping concentration of the second portion of the body region of the semiconductor layer.

A method for fabricating a semiconductor device, the method comprising:

• providing a semiconductor-on-insulator substrate including a buried insulator layer;
• forming a semiconductor layer overlying the semiconductor-on-insulator substrate, the semiconductor layer being doped with a dopant of a first conductivity type;
• forming a gate structure located on the semiconductor layer, the gate structure comprising a gate dielectric layer located on the semiconductor layer and a gate conductor layer located on the gate dielectric layer, the gate structure including a first gate portion extending in a first direction, and a second gate portion extending from the first gate portion in a second direction, which is perpendicular to the first direction;
• performing a shallow dopant implant to form a source extension region and a drain extension region in the semiconductor layer on opposite sides of the second gate portion of the gate structure, the source extension region and the drain extension region extending under the gate dielectric layer and the gate conductor layer, the source extension region and the drain extension region contacting the gate dielectric layer of the second gate portion, the source extension region and the drain extension region being doped with a dopant of a second conductivity type, which is opposite the first conductivity type;
• after forming the source extension region and the drain extension region, forming a mask comprising a first open region, a second open region, and a blocking region, the first open region exposing a first portion of the semiconductor layer, the first portion of the semiconductor layer being located at an end of the semiconductor layer that is closest to the first gate portion of the gate structure, the second open region exposing a second portion of the semiconductor layer comprising the entire drain extension region, the blocking region being formed over and blocking a third portion of the semiconductor layer, the third portion of the semiconductor layer being located at an end of the semiconductor layer that is furthest from the first gate portion of the gate structure;
• after forming the mask, performing a deep dopant implant to form a deep source region and a deep drain region in the semiconductor layer, the deep drain region contacting the drain extension region and abutting the buried insulator layer, the mask preventing a deep source region from being formed within the third portion of the semiconductor layer, the deep source region being formed in the first portion of the semiconductor layer, the deep source region contacting the source extension region and abutting the buried insulator layer, the deep drain region and the deep source region being doped with a dopant of the second conductivity type;
• after forming the deep drain region and the deep source region, removing the mask;
• forming a source metal-semiconductor alloy contact and a drain metal-semiconductor alloy contact, the drain metal-semiconductor alloy contact located on an upper portion of the deep drain region and abutting the drain extension region, the source metal-semiconductor alloy contact abutting the source extension region,
• wherein in the performing of the deep dopant implant to form the deep source region and the deep drain region, dopant is implanted into the first portion of the semiconductor layer that will underlay a first portion of the source metal-semiconductor alloy contact, but dopant is not implanted in the third portion of the semiconductor layer that will underlay a second portion of the source metal-semiconductor alloy contact so that the second portion of the source metal-semiconductor alloy contact will be located above and will directly contact the third portion of the semiconductor layer to form an internal body contact,
• the second portion of the source metal-semiconductor alloy contact is located at an end of the source metal-semiconductor alloy contact that is furthest from the first gate portion of the gate structure,
• a sidewall of the source extension region directly contacts both a sidewall of the second portion of the source metal-semiconductor alloy contact that is located above the third portion of the semiconductor layer, and a sidewall of the first portion of the source metal-semiconductor alloy contact that is located above the first portion of the semiconductor layer, and
• a doping concentration of the third portion of the semiconductor layer which directly contacts the second portion of the source metal-semiconductor alloy contact is the same as a doping concentration of another portion of the semiconductor layer that directly contacts the second gate portion of the gate structure.