Lateral double diffused metal-oxide-semiconductor device and method for fabricating the same

A method for fabricating a lateral double diffused metal oxide semiconductor (LDMOS) device, comprising:

• providing a semiconductor substrate, having a first conductivity type;
• forming an epitaxial semiconductor layer over the semiconductor substrate, having the first conductivity type;
• forming a gate structure over a portion of the epitaxial semiconductor layer;
• forming a first doped region in a portion of the epitaxial semiconductor layer adjacent to a first side of the gate structure, having the first conductivity type;
• forming a second doped region in a portion of the epitaxial semiconductor layer adjacent to a second side of the gate structure opposite to the first side, having a second conductivity type opposite to the first conductivity type;
• forming a third doped region in a portion of the first doped region, having the second conductivity type;
• forming a fourth doped region in a portion of the second doped region, having the second conductivity type opposite to the first conductivity type;
• forming an insulating layer over the second doped region, the gate structure, and a portion of the third doped region;
• forming a trench in a portion of the third doped region, and the epitaxial semiconductor layer under the first doped region adjacent to the insulating layer;
• performing an ion implantation process, implanting dopants of the first conductive type in the epitaxial semiconductor layer exposed by the trench, thereby forming a fifth doped region, wherein the fifth doping region physically contacts the semiconductor substrate and does not physically contact the first doped region;
• and
• forming a conductive contact in the trench, wherein the conductive contact physically contacts the fifth doped region.

A method for fabricating a lateral double diffused metal oxide semiconductor (LDMOS) device, comprising:

• providing a semiconductor substrate, having a first conductivity type;
• forming a first epitaxial semiconductor layer over the semiconductor substrate, having the first conductivity type;
• forming a first trench in a portion of the first epitaxial semiconductor layer;
• performing an ion implantation process, implanting dopants of the first conductive type in the first epitaxial semiconductor layer exposed by the first trench, thereby forming a first doped region, wherein the first doped region physically contacts the semiconductor substrate;
• forming a second epitaxial semiconductor layer in the first trench;
• forming a gate structure over a portion of the epitaxial semiconductor layer, adjacent to the second epitaxial semiconductor layer;
• forming a second doped region in a portion of the first epitaxial semiconductor layer adjacent to a first side of the gate structure, surrounding the second epitaxial semiconductor layer, having the first conductivity type, wherein the second doped region does not physically contact the first doped region;
• forming a third doped region in a portion of the first epitaxial semiconductor layer adjacent to a second side of the gate structure opposing to the first side, having a second conductivity type opposite to the first conductivity type;
• forming a fourth doped region in a portion of the second doped region, having the second conductivity type;
• forming a fifth doped region in a portion of the third doped region, having the second conductivity type;
• forming an insulating layer over the fourth doped region, the gate structure, and a portion of the fifth doped region;
• partially removing the second epitaxial semiconductor layer and forming a second trench, wherein the second trench partially exposes a portion of the second and fourth doped regions;
• and
• forming a conductive contact in the second trench, wherein the conductive contact physically contacts the second epitaxial semiconductor layer.