Planar vertical DMOS transistor with reduced gate charge
AssigneeMicrel, Inc.
InventorDavid Raymond Zinn
Life of this patent
Estimating the term…
Abstract
A planar vertical DMOS transistor includes a dielectric separation structure formed under the conductive gate and over the bulk of the semiconductor layer outside of the channel region of the transistor. The planar vertical DMOS transistor with a conductive gate formed over the dielectric structure reduces the parasitic gate-to-bulk or gate-to-drain overlap capacitance by increasing the separation between the conductive gate and the bulk of the semiconductor layer. Meanwhile, the desired distance between the body regions formed on opposing sides of the conductive gate is maintained.
Claims19
A planar vertical DMOS transistor comprising:
- a heavily doped semiconductor substrate of a first conductivity type forming a drain region;
- a semiconductor layer of the first conductivity type formed over the semiconductor substrate, the semiconductor layer being more lightly doped than the semiconductor substrate, the semiconductor layer forming a drain drift region;
- a dielectric structure formed on the semiconductor layer;
- a conductive gate formed on the semiconductor layer and over a top surface of the dielectric structure, portions of the conductive gate extending beyond two sides of the dielectric structure being insulated from the semiconductor layer by a gate oxide layer and portions of the conductive gate formed over the top surface of the dielectric structure being insulated from the semiconductor layer by the dielectric structure;
- a body region of a second conductivity type, opposite the first conductivity type, formed in the semiconductor layer on outer sides of the conductive gate, portions of the body region overlapping the conductive gate portions formed over the gate oxide layer to form a channel region of the DMOS transistor;
- and
- a source region of the first conductivity type formed in the body region and aligned to the outer sides of the conductive gate.
A method of forming a planar vertical DMOS transistor, comprising:
- providing a heavily doped semiconductor substrate of a first conductivity type forming a semiconductor layer of the first conductivity type on the semiconductor substrate, the semiconductor layer being more lightly doped than the semiconductor substrate, the semiconductor layer forming a drain drift region;
- forming a dielectric structure on the semiconductor layer;
- forming a gate oxide layer on the semiconductor layer;
- forming a conductive gate on the semiconductor layer and over a top surface of the dielectric structure, portions of the conductive gate extending beyond two sides of the dielectric structure being insulated from the semiconductor layer by the gate oxide layer and portions of the conductive gate formed over the top surface of the dielectric structure being insulated from the semiconductor layer by the dielectric structure;
- forming a body region of a second conductivity type, opposite the first conductivity type, in the semiconductor layer on outer sides of the conductive gate, portions of the body region overlapping the conductive gate portions formed over the gate oxide layer to form a channel region of the DMOS transistor;
- and
- forming a source region of the first conductivity type in the body region and aligned to the outer sides of the conductive gate.
Dependencies are inferred from the claim text.