Power MOSFET and methods for forming the same

A method comprising:

• epitaxially growing an epitaxy semiconductor region of a first conductivity type;
• forming a first trench in the epitaxy semiconductor region;
• forming an implantation mask extending into the trench and covering edge portions of the trench;
• forming an additional implantation mask to cover a bottom of the trench, wherein the additional implantation mask has a top surface lower than a top surface of the trench;
• performing a tilt implantation through the implantation mask and the additional implantation mask to form a Doped Drain (DD) region in the epitaxy semiconductor region, wherein the DD region comprises portions overlapped by the implantation mask, and wherein the DD region is of a first conductivity type;
• etching the epitaxy semiconductor region to extend the trench further down into the epitaxy semiconductor region, wherein the etching is performed using the implantation mask as an etching mask;
• after the etching, forming a first dielectric layer lining the trench;
• forming a field plate in the trench and over the first dielectric layer, wherein the field plate comprises a bottom and sidewalls contacting the first dielectric layer;
• forming a second dielectric layer over the field plate;
• forming a main gate in the trench and over the second dielectric layer;
• and
• forming a lateral Metal-Oxide-Semiconductor (MOS) device, wherein the lateral MOS device comprises a gate electrode over the semiconductor region.

A method comprising:

• forming a field plate in a semiconductor region of a first conductivity type;
• forming a first dielectric layer comprising first portions on opposite sides of the field plate, and second portions underlying the field plate;
• forming Doped Drain (DD) regions on opposite sides of the first dielectric layer, wherein the DD region is of the first conductivity type;
• performing an implantation to form a body region in the semiconductor region, wherein the body region is of a second conductivity type opposite to the first conductivity type;
• forming a second dielectric layer over the field plate;
• forming a main gate over the second dielectric layer, wherein the DD regions comprise a portion overlapped by the main gate, and the portion of the DD regions comprises a sidewall contacting a sidewall of the first dielectric layer, and the forming the main gate comprises:
• forming a first portion of the main gate before the implantation, with the implantation performed using the first portion as a part of a mask;
• and
• after the second dielectric layer is formed, forming a second portion of the main gate;
• and
• forming a lateral Metal-Oxide-Semiconductor (MOS) device, wherein the lateral MOS device comprises a gate electrode over the semiconductor region.