Innovative approach of 4F2 driver formation for high-density RRAM and MRAM

A memory array, comprising:

• a semiconductor body comprising a surface having alternating rows of a doped semiconductor material and a dielectric material that extend along a first direction;
• a plurality of trenches located within the surface to define a plurality of raised semiconductor structures respectively having a drain region vertically separated by a channel region from a source region extending below the plurality of trenches, wherein the plurality of trenches respectively comprise:
• a gate dielectric layer abutting a first sidewall and an opposite second sidewall of a trench;
• a first gate electrode vertically extending along the first sidewall of the trench;
• a second gate electrode spatially separated from the first gate electrode and vertically extending along the second sidewall of the trench;
• a plurality of metal contacts disposed within a dielectric layer overlying the semiconductor body and configured to couple the drain region to a data storage element configured to store data;
• an isolation dielectric material disposed within the plurality of trenches at positions that vertically abut to surfaces of the first and second gate electrodes and that laterally abut sidewalls of the first and second gate electrodes;
• and
• wherein entire surfaces of the first gate electrode and the second gate electrode abutting the gate dielectric layer are tapered at an oblique angle with respect to a bottom surface of the trench.

A memory array, comprising:

• a semiconductor body having a first trench and a second trench that form a raised semiconductor structure having a source region and a drain region vertically separated by a channel region, wherein the first trench and the second trench have sidewalls that are tapered from a top of the raised semiconductor structure to a depth that is greater than that of the channel region;
• a gate dielectric layer having a substantially uniform thickness, which is disposed along sidewalls and bottom surfaces of the first and second trenches;
• a first gate electrode disposed within the first trench at a first position abutting the gate dielectric layer along a first sidewall of the first trench;
• a second gate electrode disposed within the second trench at a second position abutting the gate dielectric layer along a first sidewall of the second trench;
• and
• an isolation dielectric material disposed within the first and second trenches at positions that vertically abut top surfaces of the first and second electrodes and that laterally abut sidewalls of the first and second gate electrodes,
• wherein entire surfaces of the first gate electrode and the second gate electrode facing the raised semiconductor structure are tapered at an oblique angle with respect to the bottom surfaces of the first and second trenches.