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US 9,178,038 B2Granted
Raised source/drain MOS transistor and method of forming the transistor with an implant spacer and an epitaxial spacer
AssigneeTexas Instruments Incorporated
InventorsSeung-Chul Song, James W. Blatchford, Kwan-Yong Lim
Life of this patent
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Abstract
A raised source/drain MOS transistor is formed in a process that utilizes a first sidewall spacer when implanting a semiconductor region to form the heavily-doped source region and the heavily-doped drain region of the transistor, and a second different sidewall spacer when epitaxially growing the raised source region and the raised drain region of the transistor.
Claims3
A method of forming a semiconductor structure comprising:
- forming a gate structure that includes a gate dielectric that touches and lies above a semiconductor region, and a gate that touches and lies above the gate dielectric;
- implanting the semiconductor region after the gate structure has been formed to form a lightly-doped source region and a lightly-doped drain region that touch the semiconductor region;
- forming a first sidewall spacer that touches and laterally surrounds the gate structure;
- implanting the semiconductor region, the lightly-doped source region, and the lightly-doped drain region after the first sidewall spacer has been formed to form a heavily-doped source region and a heavily-doped drain region, the heavily-doped source region touching the semiconductor region and the lightly-doped source region, the heavily-doped drain region touching the semiconductor region and the lightly-doped drain region;
- forming a second sidewall spacer that touches and laterally surrounds the gate structure after the heavily-doped source region and the heavily-doped drain region have been formed;
- epitaxially growing a raised source region that touches the heavily-doped source region, and a raised drain region that touches the heavily-doped drain region after the second sidewall spacer has been formed;
- and
- removing the first sidewall spacer after the heavily-doped source region and the heavily-doped drain region have been formed and before the second sidewall spacer is formed.
5 more elements
A method of forming a semiconductor structure comprising:
- forming a gate structure that includes a gate dielectric that touches and lies above a semiconductor region, and a gate that touches and lies above the gate dielectric;
- implanting the semiconductor region after the gate structure has been formed to form a lightly-doped source region and a lightly-doped drain region that touch the semiconductor region;
- forming a first sidewall spacer that touches and laterally surrounds the gate structure;
- implanting the semiconductor region, the lightly-doped source region, and the lightly-doped drain region after the first sidewall spacer has been formed to form a heavily-doped source region and a heavily-doped drain region, the heavily-doped source region touching the semiconductor region and the lightly-doped source region, the heavily-doped drain region touching the semiconductor region and the lightly-doped drain region;
- forming a second sidewall spacer that touches and laterally surrounds the gate structure after the heavily-doped source region and the heavily-doped drain region have been formed;
- and
- epitaxially growing a raised source region that touches the heavily-doped source region, and a raised drain region that touches the heavily-doped drain region after the second sidewall spacer has been formed;
- wherein forming the second sidewall spacer includes forming a third sidewall spacer to touch and laterally surround the first sidewall spacer, a combination of the first sidewall spacer and the third sidewall spacer forming the second sidewall spacer, and
- wherein the heavily-doped source region has a width, the raised source region has a width, and the width of the heavily-doped source region is substantially greater than the width of the raised source region.
6 more elements
Dependencies are inferred from the claim text.