Methods of forming transistor devices with different threshold voltages and the resulting products

A method of forming replacement gate structures for first and second NMOS transistor devices and third and fourth PMOS transistor devices, comprising:

• performing at least one etching process to remove sacrificial gate structures for said first, second, third and fourth transistor devices to thereby define first, second third and fourth gate cavities for said first, second, third and fourth transistor devices, respectively, said first, second, third and fourth gate cavities being laterally defined by sidewall spacers;
• forming a high-k oxide gate insulation layer in said first, second, third and fourth gate cavities for said first, second, third and fourth transistor devices;
• forming a conformal patterned masking layer that covers said high-k oxide gate insulation layer in said second and third gate cavities while exposing said high-k oxide gate insulation layer in said first and fourth gate cavities;
• forming a metal oxide material layer on said high-k oxide gate insulation layer in said first and fourth gate cavities and on said conformal patterned masking layer that is positioned within said second and third gate cavities;
• performing at least one recess etching process such that first and fourth portions of said high-k oxide gate insulation layer and first and fourth portions of said metal oxide layer are positioned entirely within said first and fourth gate cavities, respectively, while second and third portions of said high-k oxide gate insulation layer, first and second portions of said conformal patterned masking layer and second and third portions of said metal oxide layer are positioned entirely within said second and third gate cavities, resprectively;
• forming a conformal capping layer above materials within said first, second, third and fourth gate cavities;
• performing at least one heating process to drive metal material from said metal oxide layer into said first and fourth portions of said high-k oxide gate insulation layer in said first and fourth gate cavities to thereby form first and second composite metal-high-k oxide alloy gate insulation layers in said first and fourth gate cavities, respectively, while preventing metal from said metal oxide material layer from being driven into said second and third portions of said high-k oxide gate insulation layer in said second and third gate cavities, respectively, during said at least one heating process;
• removing said conformal capping layer;
• removing at least said first and second portions of said conformal patterned masking layer from within said second and third gate cavities;
• and
• performing at least one process operation to form first, second, third and fourth gate electrode structures in said first, second, third and fourth gate cavities.