US 9,178,024 B2 · Thin film transistor display panel and manufacturing method thereof

Abstract

A method for manufacturing a thin film transistor array panel includes forming a gate line and a gate electrode protruding from the gate line on a substrate; forming a gate insulating layer on the gate line and the gate electrode; depositing sequentially a semiconductor material and a metal material on the gate insulating layer; performing a first etching operation on the semiconductor material and the metal material using a first mask to form a semiconductor layer and a metal layer, the metal layer including a data line, a source electrode, and a drain electrode, in which the drain electrode protrudes from the data line, and the source electrode and the drain electrode having an integral shape; and performing a second etching operation on the metal layer using a second mask to divide the source electrode and the drain electrode.

Drawings

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Drawings

Claims17

Dependent claims

A method for manufacturing a thin film transistor array panel, comprising:

forming a gate line and a gate electrode protruding from the gate line on a substrate;
forming a gate insulating layer on the gate line and the gate electrode;
depositing a semiconductor material on the gate insulating layer;
depositing a metal material directly on the semiconductor material;
performing a first etching operation on the semiconductor material and the metal material using a first mask to form a semiconductor layer and a metal layer, the metal layer comprising a data line, a source electrode, and a drain electrode,
wherein the drain electrode protrudes from the data line, the source electrode is formed on the gate electrode, the source electrode and the drain electrode have an integral shape, and the semiconductor layer is positioned under the metal layer;
performing a second etching operation on the metal layer using a second mask to divide the source electrode and the drain electrode;
and
forming a pixel electrode connected to the drain electrode,
wherein performing the first etching operation comprises:
forming a first photosensitive film on the metal material;
processing the first photosensitive film using the first mask to form a first photosensitive film pattern;
and
forming the data line, the source electrode, and the drain electrode using the first photosensitive film pattern, wherein performing the second etching operation comprises:
forming a second photosensitive film directly on the data line, the source electrode, and the drain electrode;
processing the second photosensitive film using the second mask to form a second photosensitive film pattern;
and
dividing the source electrode and the drain electrode using the second photosensitive film pattern so as to form a channel in the semiconductor layer,
wherein the second photosensitive film pattern covers an upper portion of the source electrode and the drain electrode without covering the channel, and covers a side portion of the source electrode, the drain electrode, and the semiconductor layer,
wherein only the metal layer is etched during the second etching operation,
wherein the semiconductor material comprises an oxide semiconductor,
wherein the gate insulating layer has a multilayer structure comprising a silicon oxide layer and a silicon nitride layer, the gate electrode contacting the silicon nitride layer, and the semiconductor layer contacting the silicon oxide layer,
wherein the semiconductor layer consists of a single material.

20 more elements

A method for manufacturing a thin film transistor array panel, comprising:

forming a gate line and a gate electrode protruding from the gate line on a substrate;
forming a gate insulating layer on the gate line and the gate electrode and entirely covering the substrate;
depositing sequentially a semiconductor material and a metal material on the gate insulating layer;
executing a first etching operation for etching the metal material using a first mask to remove a portion of the metal material overlapping the gate electrode;
executing a second etching operation, after executing the first etching operation, for etching the semiconductor material and the metal material using a second mask to form a semiconductor layer and a metal layer, the metal layer comprising a data line, a source electrode overlapping the gate electrode and protruding from the data line, and a drain electrode,
wherein the drain electrode is spaced apart from the source electrode, and the semiconductor layer is positioned under the metal layer;
and
forming a pixel electrode connected to the drain electrode,
wherein executing the first etching operation comprises:
forming a first photosensitive film on a portion of the metal material that will form the data line, the source electrode, and the drain electrode;
processing the first photosensitive film using the first mask to form a first photosensitive film pattern;
and
dividing a portion of the metal material that will form the source electrode and a portion of the metal material that will form the drain electrode using the first photosensitive film pattern so as to form a channel in the semiconductor layer, wherein the first photosensitive film pattern covers an upper portion of the portion of the metal material that will form the source electrode and the portion of the metal material that will form the drain electrode without covering the channel,
wherein only the metal material is etched during the first etching operation,
wherein the semiconductor material comprises an oxide semiconductor,
wherein the gate insulating layer has a multilayer structure comprising a silicon oxide layer and a silicon nitride layer, the gate electrode contacting the silicon nitride layer, and the semiconductor layer contacting the silicon oxide layer, and
wherein the semiconductor layer consists of a single material.

14 more elements

A method for manufacturing a thin film transistor array panel, comprising:

forming a gate line and a gate electrode protruding from the gate line on a substrate;
forming a gate insulating layer on the gate line and the gate electrode;
depositing a semiconductor material on the gate insulating layer;
depositing a metal material directly on the semiconductor material;
forming a first photosensitive film pattern, using a first mask, on the metal material and the semiconductor material;
etching the semiconductor material and the metal material, having the first photosensitive film pattern disposed thereon, to form a semiconductor layer and a metal layer, the metal layer comprising a data line, a source electrode, and a drain electrode, the source electrode being integrally formed with the drain electrode;
removing the first photosensitive film pattern;
forming a second photosensitive film pattern, using a second mask, directly on the metal layer;
etching the metal layer, having the second photosensitive film pattern disposed thereon, thereby separating the source electrode and the drain electrode, without etching the semiconductor material;
removing the second photosensitive film pattern;
forming a passivation layer on the source electrode and the drain electrode;
and
forming a pixel electrode, the pixel electrode being connected to the drain electrode via a contact hole in the passivation layer,
wherein the semiconductor material comprises an oxide semiconductor,
wherein the gate insulating layer has a multilayer structure comprising a silicon oxide layer and a silicon nitride layer, the gate electrode contacting the silicon nitride layer, and the semiconductor layer contacting the silicon oxide layer, and
wherein the semiconductor layer consists of a single material.

13 more elements

Dependencies are inferred from the claim text.

Description5,844 words

Summary1,389 words

#This application claims priority to and the benefit of Korean Patent Application No. 10-2011-0132994, filed on Dec. 12, 2011, the entire contents of which are incorporated herein by reference.

#1. Field

#The following description relates to a thin film transistor array panel and a manufacturing method thereof. More particularly, the description relates to a thin film transistor array panel and a manufacturing method for reducing skew formed during an etching process.

Brief description of the drawings16 figures

#The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention, and together with the description serve to explain the principles of the invention.

#FIG. 1 is a top plan view of a pixel of a thin film transistor array panel according to an exemplary embodiment of the present invention.

#FIG. 2 is a cross-sectional view taken along the lines II-II and II′-II′ of FIG. 1.

Detailed description4,052 words

#The invention will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways without departing from the spirit or scope of the invention.

#In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like reference numerals designate like elements throughout the specification. It will be understood that for the purposes of this disclosure, “at least one of X, Y, and Z” can be construed as X only, Y only, Z only, or any combination of two or more items X, Y, and Z (e.g., XYZ, XZ, XYY, YZ, ZZ). Further, it will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

#A thin film transistor array panel according to exemplary embodiments of the invention will be described with reference to accompanying drawings.

Facts

Application

13/464,613Filed 4 May 2012

Priority

KR 10-2011-013299412 Dec 2011

Published

US 2013/0146864 A113 Jun 2013

Granted

3 Nov 2015

Term ends

4 May 2032

Estimated · how

20 years from earliest known nonprovisional domestic filing plus recorded patent term adjustment. Maintenance-fee lapses, terminal disclaimers and statutory extensions have not been checked. The continuity chain may be incomplete; this is not an enforceability determination.

Classification9 codes

H10D 30/6729
Thin-film transistors [TFT]: characterised by the electrodes
H10D 30/0316
Characterised by the gate electrodes: of lateral bottom-gate TFTs comprising only a single gate
H10D 30/0321
Of thin-film transistors [TFT]: comprising silicon, e.g. amorphous silicon or polysilicon
H10D 30/6757
Thin-film transistors [TFT]: characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile

Timeline

12 Dec 2011Priority claimedKR 10-2011-0132994
4 May 2012Application filedUS 13/464,613
7 May 2012Assigned to Samsung Display Co., Ltd.assignment of assignor's interest
13 Jun 2013PublishedUS 2013/0146864 A1
3 Nov 2015GrantedUS 9,178,024 B2
12 Oct 2026TodayWithin its term
4 May 2032Term endsEstimated

Thin film transistor display panel and manufacturing method thereof

Life of this patent

Thin film transistor display panel and manufacturing method thereof

Life of this patent

Life of this patent

Abstract

Drawings

Drawings

Claims17

Description5,844 words

Drawings

Description5,844 words

Classification9 codes

Life of this patent