Fin isolation in multi-gate field effect transistors

#The present invention relates to field effect transistors, and more specifically, to multi-gate field effect transistors. Multi-gate field effect transistors (FETs) often include a semiconductor fin or similar structure arranged on a substrate. The fin partially defines active regions (source and drain regions) and a channel region of the device. The geometry of the fin provides a multi-gate FET device.

#One method for fabricating multi-gate FETs such as FinFETs includes patterning a number of fins on a substrate. Once the fins are patterned, a dummy gate stack that includes a polysilicon material is patterned over portions of the fins. The dummy gate stack may be formed by a material deposition process followed by a patterning and etching process. The dummy gate stack defines the channel regions of the FETs. The active regions may be increased in size and connected to adjacent fins by performing an epitaxial growth process that grows epitaxial semiconductor material from the fins. Once the active regions are formed and doped either during the epitaxial growth process or with an ion implantation process, the dummy gate stack may be removed, and the gate stack may be formed over the channel regions of the fins.

#In previous fabrication processes, a number of fins are patterned with substantially equal spacing between the fins. In order to fabricate multi-FET devices that each includes a plurality of fins, one or more fins may be removed from the substrate to isolate each of the multi-FET devices.

#The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

#FIG. 1 illustrates a perspective view of a prior art example of multi-FET devices in fabrication.

#FIG. 2 illustrates a side view of a substrate, a semiconductor layer, and a hardmask layer.

#The prior art example of a fin and dummy gate stack arrangement illustrated in FIG. 1 includes an undesirable depression 112 or reduction in the height of the dummy gate stack 104 in regions of the substrate 101 that do not include fins 102. The methods and illustrated embodiments discussed below offer a solution that avoids forming an undesirable dip and provide a dummy gate stack that has a substantially more uniform height when formed over semiconductor fins and isolation regions arranged between FET devices. The improved dummy gate stack provides improved multi-FET devices.

#In this regard, FIG. 2 illustrates a side view of a substrate 202, a semiconductor layer 204 arranged on the substrate, and a hardmask layer 206 arranged on the semiconductor layer 204. The substrate 202 of the illustrated embodiment includes an insulator material such as, for example, a buried oxide layer of a semiconductor-on-insulator wafer. Alternate embodiments may include a substrate 202 that includes a bulk semiconductor material such as, for example, a silicon or a germanium material. In such alternate embodiments, the fins 304 (described below) may be formed from the bulk semiconductor material. The semiconductor layer 204 may include any semiconductor material such as, for example, a silicon material or a germanium material. The hardmask layer 206 may include a hardmask material such as, for example, an oxide or a nitride material. In the illustrated embodiment, the hardmask layer 206 includes a nitride material.

#FIG. 3 illustrates a top view of the resultant structure following the patterning and etching of a plurality of semiconductor fins 302. The semiconductor fins 302 may be formed by, for example, a lithographic patterning process followed by an etching process such as, reactive ion etching (RIE) that removes exposed portions of the hardmask layer 206 and the semiconductor layer 204 to expose portions of the substrate 202. FIG. 4 illustrates a side cut away view along the line 4 (of FIG. 3).