Semiconductor device and method for manufacturing same

#This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2013-171305 filed on Aug. 21, 2013, the disclosure of which are incorporated herein in its entirety by reference.

#1. Field of the Invention

#The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

#The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:

#FIG. 1 is a plan view illustrating a semiconductor device according to the first exemplary embodiment.

#FIG. 2 is a cross-sectional view illustrating a semiconductor device according to the first exemplary embodiment.

#In the drawings, numerals have the following meanings, 1: semiconductor substrate, 1a: active region, 2: isolation region, 2a, 52: silicon nitride film, 2b, 51, 58a, 58b: silicon oxide film, 3: P well, 4: N well, 5a, 5b: silicon oxide film, 6a, 6b: hafnium oxide film (first high-dielectric insulating film), 6c: aluminum oxide film (second high-dielectric insulating film), 7a, 7b: first metal film, 8a, 8b, 11, 11a, 11b, 11c, 11d: impurity-containing polysilicon film, 10a, 10b, 10c, 10d: end, 12, 12a, 12b, 12c, 12d: second metal film, 13: trench portion, 14: seam (concave portion), 15: silicon nitride film, 15a: buried insulating film, 15b: second insulating film, 15c: first insulating film, 17a: first gate electrode, 17b: second gate electrode, 19a, 19b: LDD region, 20, 25a, 25b: wiring, 20a: conductive part, 20′: third wiring, 21a: first source and drain, 21b: second source and drain, 22: SOD film, 24: contact plug, 25c, 25d: fourth wiring, 25e: fifth wiring, 26a: offset spacer, 26b: sidewall spacer, 30: word line (buried gate electrode), 30′: dummy word line, 30a: barrier metal film, 30b: metal gate film, 31: bit line, 32a: capacitor contact region, 32b, 32d: capacitor contact plug, 32c: capacitor contact pad, 33: bit contact region, 37: third gate insulating film, 38a: liner film, 38b: SOD film, 39: bit contact interlayer insulating film, 43: liner film, 45: stopper film, 48: capacitor, 48a: lower electrode, 48b: capacitor insulating film, 48c: upper electrode, 55: trench, 60: first direction, Cn: region for forming NMOS, Cp: region for forming PMOS, Tr1: first transistor, Tr2: second transistor, and Tr3: third transistor.

#The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.

#In one example of a semiconductor device and the manufacturing method thereof according to the present invention, a concave third wiring is disposed on an isolation region. In addition, a buried insulating film superior in coverage (step coverage) is formed so as to fill the concave portion of the third wiring. Consequently, even if a plurality of fourth wirings are formed on the buried insulating film, the third wiring and the fourth wirings are isolated from each other by the buried insulating film. Thus, it is possible to prevent a plurality of adjacent fourth wirings from short-circuiting to one another through the third wiring to degrade device characteristics.