Back to results
US 9,178,016 B2Granted
Charge protection for III-nitride devices
AssigneeInfineon Technologies Austria AG
InventorsMatthias Strassburg, Roman Knoefler
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeInfineon Technologies Austria AG
InventorsMatthias Strassburg, Roman Knoefler
Estimating the term…
A semiconductor device includes a III-nitride semiconductor substrate having a two-dimensional charge carrier gas at a depth from a main surface of the III-nitride semiconductor substrate. A surface protection layer is provided on the main surface of the III-nitride semiconductor substrate. The surface protection layer has charge traps in a band gap which exist at room temperature operation of the semiconductor device. A contact is provided in electrical connection with the two-dimensional charge carrier gas in the III-nitride semiconductor substrate. A charge protection layer is provided on the surface protection layer. The charge protection layer includes an oxide and shields the surface protection layer under the charge protection layer from radiation with higher energy than the bandgap energy of silicon nitride.
A semiconductor device, comprising:
A method of manufacturing a semiconductor device, the method comprising:
A semiconductor device, comprising:
A semiconductor device, comprising:
A method of manufacturing a semiconductor device, the method comprising:
A method of manufacturing a semiconductor device, the method comprising:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
From the US filing history. Foreign family members aren’t listed.
Constructional design considerations for preventing surface leakage or controlling electric field concentration: for preventing surface leakage…
Manufacture or treatment: of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels: having two-dimensional [2D] charge…
High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]: having wider bandgap layer formed on top of lower bandgap…
About 6 years 4 months of term left · ends 1 Mar 2033 (estimated)
The instant application relates to III-nitride devices, more particularly to III-nitride devices with charge protection.
GaN devices typically include a barrier region, such as AlGaN or InAlGaN, formed on a GaN buffer to automatically form a two-dimensional (2D) charge carrier gas channel near the barrier-buffer interface. The channel is formed by a 2D electron gas for n-channel devices and by a 2D hole gas for p-channel devices. In the fabrication of such GaN devices, a shift in the threshold voltage of the transistors can occur for various reasons. A threshold voltage shift results in an increase in the variation of the threshold voltage across the wafer, reducing yield.
One cause of threshold voltage shift in GaN devices is the so-called charging of the silicon nitride (SiN) layer typically formed on the surface of the barrier region in order to prevent oxidation of the barrier surface. Charging involves the storage and generation of charge traps in the silicon nitride layer. These charge traps shift the device threshold voltage when the silicon nitride layer is interposed between the active semiconductor region and certain metallizations, such as the gate structure. Electron and hole traps can arise in silicon nitride at point defects such as paramagnetic defects (e.g. ≡Si., ≡Si—O—O., ≡Si2N.), diamagnetic defects (e.g. ≡Si—Si≡, ═N—H), two coordinated Si-atoms with lone pair electrons (e.g. ═Si:), neutral defects (e.g. ≡SiO., ≡SiOH), charged defects (e.g. ≡Si., +Si≡), intrinsic defects (e.g. ≡Si., ═N—N═, ≡Si—O—O—Si≡) and extrinsic defects (e.g. ≡SiH, ≡Si2NH, ≡SiOH). Electron and hole traps can also arise in silicon nitride in the presence of existing residual Si—H bonds (so-called silicon-hydrogen-complexes), due to the polarity of the Si—H binding. The formation of silicon nitride produces residual hydrogen in the silicon nitride, forming the Si—H bonds, which have a localized hydrogen valence electron in a covalent bond between a hydrogen and silicon atom. Si—H bonds have a relatively deep energy trap level and, therefore, the resulting charge traps are stable at room temperature.
The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts. In the drawings:
FIG. 1 illustrates a cross-sectional view of an embodiment of a semiconductor die having a III-nitride semiconductor substrate and an charge protection layer;
FIG. 2 illustrates a band gap diagram of the charge protection layer included in the device of FIG. 1, with a step-wise graded oxygen concentration;
The embodiments described next prevent, or at least significantly reduce, charging of a surface protection layer formed on the surface of an III-nitride substrate by providing a charge protection layer on the surface protection layer. The charge protection layer comprises an oxide such as a metal oxide and/or silicon oxynitride, and shields the surface protection layer under the charge protection layer from radiation with higher energy than the bandgap energy of silicon nitride (e.g. ultraviolet light). This in turn prevents additional charge carriers from being stored in the surface protection layer, and also prevents defects such as point defects from being produced in the surface protection layer. Due to the charge protection layer, negative impact of charging, e.g. shift of threshold voltage, is avoided or significantly reduced. The charge protection layer can be provided before or after final passivation of the semiconductor device.
FIG. 1 illustrates a partial cross-sectional view of a semiconductor device according to an embodiment. The semiconductor device includes a III-nitride semiconductor substrate 100. The III-nitride substrate 100 incorporates a junction between two materials with different band gaps (i.e. a heterojunction) as the channel 102. For example, GaN may be combined with AlGaN or AlInGaN to form the channel 102. The III-nitride substrate 100 may have AlInN/AlN/GaN barrier/spacer/buffer layer structures. The III-nitride semiconductor substrate 100 can include a semiconductor wafer 104 and one or more epitaxial layers 106 grown on the wafer 104. The growth wafer 104 can be thinned or entirely removed later in processing, if desired. In the case of a GaN substrate 100, one or more nucleation and/or transition layers 108 can be grown on the wafer 104 followed by a GaN buffer region 110 which can include, e.g. AlN/AlGaN/GaN. A GaN alloy barrier region 112 is then grown on the GaN buffer region 110.
In general with GaN technology, the presence of polarization charges and strain effects result in the realization of a two-dimensional charge carrier gas 114 which is a two-dimensional electron or hole inversion layer characterized by very high carrier density and carrier mobility. Such a two-dimensional charge carrier gas 114, such as a 2DEG (two-dimensional electron gas) or 2DHG (two-dimensional hole gas), forms a conductive channel region 102 of the semiconductor device near the interface between the GaN alloy (e.g. AlN or AlGaN) barrier region 112 and the GaN buffer region 110 at a depth from a main surface 101 of the III-nitride semiconductor substrate 100. The thickness of the GaN alloy barrier region 112 preferably is larger than 2 nm, larger than 5 nm, or even larger than 10 nm, but does not exceed 100 nm. The Al content in the GaN alloy barrier region 112 preferably is at least sufficiently high to prevent from thermal emission across the band offset to GaN. A thin, e.g. 1-2 nm, AlN layer can be provided between the GaN buffer region 110 and the GaN alloy barrier region 112 to minimize alloy scattering and enhance 2DEG mobility. In general, any III-nitride based heterostructure can be used where a band discontinuity is responsible for the device concept and one or more two-dimensional charge carrier gases 114 can be provided.