Vertical interconnect structure, memory device and associated production method

A memory device comprising:

• a semiconductor substrate having insular active regions;
• at least one memory element formed on each insular active region for storing items of information;
• and
• at least one selection transistor formed on each insular active region for selecting the at least one memory element via at least one word line and for reading/writing the information via at least one bit line connected to the at least one memory element via the at least one selection transistor,
• wherein an electrically conductive nanoelement connects the memory element to the selection transistor and the entire bit line is embedded in a dielectric layer of the memory device;
• wherein the nanoelement is connected to the selection transistor via a metal-semiconductor compound material;
• and
• wherein the source/drain regions are defined in a self-aligned manner in respective insular active regions by means of at least one word line which divides the respective insular active regions into at least two partial regions with regard to a plan view, and wherein a first insular active region divided by one or more first word lines overlaps a second insular active region divided by one or more second word lines which are different from the one or more first word lines in a view along a direction of the first and second word lines.