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US 9,177,981 B2Granted
Solid-state imaging device having a metallic pad periphery guard ring
AssigneeSony Corporation
InventorKenichi Nishizawa
Life of this patent
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Abstract
Disclosed herein is a solid-state imaging device including: a sensor element having a plurality of pixels each having a photoelectric conversion section; and a logic element attached to the sensor element in such a manner as to be stacked on the sensor element face-to-face and provided with a pad electrode. In a stacked body of the sensor and logic elements, a pad opening is provided above the top surface of the pad electrode facing the sensor element, and a pad periphery guard ring is provided to surround the side portion of the pad opening. The pad periphery guard ring is formed by integrally filling, on the side of the pad opening, an entire trench that is at least as deep as the pad opening with a metal material.
Claims16
A solid-state imaging device comprising:
- a sensor element interconnect layer between a sensor element semiconductor substrate and a logic element interconnect layer, said logic element interconnect layer being between a logic element semiconductor substrate and said sensor element interconnect layer;
- semiconductor devices in said sensor element semiconductor substrate, a chip periphery trench encircling said semiconductor devices in a top view of the solid-state imaging device;
- a first metallic chip periphery guard ring in said chip periphery trench, said chip periphery trench extending though said sensor element semiconductor substrate and said sensor element interconnect layer;
- a second metallic chip periphery guard ring in said logic element interconnect layer, said chip periphery trench terminating at said second metallic chip periphery guard ring;
- a first metallic pad periphery guard ring in a pad periphery trench, said pad periphery trench extending though said sensor element semiconductor substrate and said sensor element interconnect layer;
- a second metallic pad periphery guard ring in said logic element interconnect layer, said pad periphery trench terminating at said second metallic pad periphery guard ring.
3 more elements
A solid-state imaging device comprising:
- a sensor element interconnect layer between a sensor element semiconductor substrate and a logic element interconnect layer, said logic element interconnect layer being between a logic element semiconductor substrate and said sensor element interconnect layer;
- semiconductor devices in said sensor element semiconductor substrate, a chip periphery trench encircling said semiconductor devices in a top view of the solid-state imaging device;
- a first metallic chip periphery guard ring in said chip periphery trench, said chip periphery trench extending though said sensor element semiconductor substrate and said sensor element interconnect layer;
- a second metallic chip periphery guard ring in said logic element interconnect layer, said chip periphery trench terminating at said second metallic chip periphery guard ring;
- a first metallic pad periphery guard ring in a pad periphery trench, said pad periphery trench extending though said sensor element semiconductor substrate and said sensor element interconnect layer,
- a pad opening extending though said sensor element semiconductor substrate and said sensor element interconnect layer, said pad periphery trench encircling said pad opening in said top view of the solid-state imaging device,
- wherein said pad opening terminates in said logic element interconnect layer at a pad electrode.
4 more elements
A solid-state imaging device comprising:
- a sensor element interconnect layer between a sensor element semiconductor substrate and a logic element interconnect layer, said logic element interconnect layer being between a logic element semiconductor substrate and said sensor element interconnect layer;
- semiconductor devices in said sensor element semiconductor substrate, a chip periphery trench encircling said semiconductor devices in a top view of the solid-state imaging device;
- a first metallic chip periphery guard ring in said chip periphery trench, said chip periphery trench extending though said sensor element semiconductor substrate and said sensor element interconnect layer;
- a second metallic chip periphery guard ring in said logic element interconnect layer, said chip periphery trench terminating at said second metallic chip periphery guard ring;
- a first metallic pad periphery guard ring in a pad periphery trench, said pad periphery trench extending though said sensor element semiconductor substrate and said sensor element interconnect layer,
- a pad opening extending though said sensor element semiconductor substrate and said sensor element interconnect layer, said pad periphery trench encircling said pad opening in said top view of the solid-state imaging device,
- wherein said pad opening is wider in said sensor element semiconductor substrate than in said logic element interconnect layer.
4 more elements
Dependencies are inferred from the claim text.