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US 9,177,964 B2Granted
Methods of forming sidewall gates
AssigneeSanDisk 3D LLC
InventorsAkira Nakada, Michiaki Sano, Naohito Yanagida, Teruyuki Mine
Life of this patent
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Abstract
A method of forming sidewall gates for vertical transistors includes depositing a gate dielectric layer over polysilicon channel structures, and depositing a gate polysilicon layer over the gate dielectric. The gate polysilicon layer is then etched back to form separated gate electrodes. Filler portions are then formed between gate electrodes, which are then etched from the top down while their sides are protected.
Claims19
A method of forming a three dimensional memory array comprising:
- forming a plurality of vertical polysilicon structures;
- subsequently depositing a dielectric layer on sidewalls of the plurality of vertical polysilicon structures;
- subsequently depositing a polysilicon gate layer on the dielectric layer on sidewalls of the plurality of vertical polysilicon structures;
- subsequently etching back the polysilicon gate layer to form separate polysilicon gate electrodes;
- subsequently forming filler portions between the polysilicon gate electrodes, the filler portions covering sides of the polysilicon gate electrodes and exposing tops of the polysilicon gate electrodes;
- subsequently etching the polysilicon gate electrodes from the exposed tops downwards while the filler portions cover sides of the polysilicon gate electrodes;
- wherein the plurality of vertical polysilicon structures are formed on a plurality of global bit lines that extend horizontally along a first direction;
- and
- wherein a barrier layer is formed between the plurality of global bit lines and the vertical polysilicon structures.
6 more elements
A method of forming a vertical transistor comprising:
- forming a vertical polysilicon structure;
- subsequently depositing a dielectric layer on sidewalls of the vertical polysilicon structure;
- subsequently depositing a polysilicon gate layer on the dielectric layer on sidewalls of the vertical polysilicon structure;
- subsequently etching back the polysilicon gate layer to form separate polysilicon gate electrodes;
- subsequently forming filler portions covering sides of the polysilicon gate electrodes and exposing tops of the polysilicon gate electrodes;
- subsequently etching the polysilicon gate electrodes from the exposed tops downwards while the filler portions cover sides of the polysilicon gate electrodes;
- and
- subsequently forming vertical bit lines extending up from the vertical polysilicon structures.
5 more elements
Dependencies are inferred from the claim text.