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US 9,177,961 B2Granted
Wafer with intrinsic semiconductor layer
AssigneeSoitec
InventorsNicolas Daval, Cécile Aulnette, Bich-Yen Nguyen
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Abstract
The present disclosure relates to a method for the manufacture of a wafer by providing a doped layer on a semiconductor substrate; providing a first semiconductor layer on the doped layer; providing a buried oxide layer on the first semiconductor layer; and providing a second semiconductor layer on the buried oxide layer to form a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer. The disclosure also relates to the wafer that is produced by the new method.
Claims17
A method for manufacturing a semiconductor device, comprising:
- growing a doped layer on a semiconductor substrate;
- growing an intrinsic first semiconductor layer on the doped layer;
- providing an oxide layer on the intrinsic first semiconductor layer;
- providing a second semiconductor layer on the oxide layer to form a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer;
- forming an embedded DRAM device in a first region of the wafer;
- and
- forming a back-biased transistor in a second region of the wafer different from the first region of the wafer, forming the back-biased transistor comprising forming a back-biasing region in the intrinsic first semiconductor layer by doping at least a portion of the intrinsic first semiconductor layer with n or p dopants.
4 more elements
Dependencies are inferred from the claim text.