Field effect transistor (FET) with self-aligned contacts, integrated circuit (IC) chip and method of manufacture
AssigneeGlobalfoundries Inc.
InventorsSzu-Lin Cheng, Jack O. Chu, Isaac Lauer, Jeng-Bang Yau
Life of this patent
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Abstract
Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations and adjacent source/drain regions are defined on a semiconductor wafer, e.g., a silicon on insulator (SOI) wafer. Source/drains are formed in source/drains regions. A stopping layer is formed on source/drains. Contact spacers are formed above gates. Source/drain contacts are formed to the stopping layer, e.g., after converting the stopping layer to silicide. The contact spacers separate source/drain contacts from each other.
Claims17
A method of forming Field Effect Transistors (FETs), said method comprising:
- defining FET locations on a semiconductor wafer;
- forming gates in said FET locations, source/drain regions being defined adjacent to said gates;
- forming source/drains in said source/drain regions;
- forming a stopping layer on said source/drains;
- forming a sacrificial layer on said stopping layer, said sacrificial layer extending from said stopping layer above said gates;
- forming contact spacers in spaces in said sacrificial layer above said gates;
- and
- forming source/drain contacts to said stopping layer, wherein forming said source/drain contacts comprises:
- removing said sacrificial layer, a contact spacer remaining on each of said gates, said stopping layer being re-exposed above said source/drain regions, and
- converting re-exposed said stopping layer to silicide.
A method of forming CMOS Integrated Circuit (IC) chips, said method comprising:
- defining Field Effect Transistor (FET) locations on a semiconductor wafer;
- forming gates in defined said FET locations;
- forming source/drains adjacent to said gates;
- forming a stopping layer on said source/drains;
- growing a sacrificial layer on said semiconductor wafer, said sacrificial layer extending from said stopping layer above said gates;
- forming contact spacers in spaces in said sacrificial layer above said gates;
- converting said stopping layer to silicide;
- forming source/drain contacts to the silicided source/drains, wherein forming said source/drain contacts comprises:
- removing said sacrificial layer, said contact spacers remaining on said conformal capping layer above said gates, said stopping layer being re-exposed above said source/drain regions, and
- converting re-exposed said stopping layer to silicide;
- and
- forming chip wiring connecting said FETs into chip circuits and connecting said chip circuits together.
Dependencies are inferred from the claim text.