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US 9,177,951 B2Granted
Three-dimensional electrostatic discharge semiconductor device
AssigneeGlobalfoundries Inc.
InventorsJagar Singh, Andy Wei, Mahadeva Iyer Natarajan
Life of this patent
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Abstract
Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.
Claims12
A semiconductor device, comprising:
- a semiconductor substrate;
- at least one raised semiconductor structure coupled to the substrate, the at least one raised structure having a width of about 5 nm to about 50 nm;
- and
- at least one electrostatic discharge (ESD) semiconductor device situated at a top portion of the at least one raised structure, wherein the at least one ESD device comprises a diode, and wherein the diode comprises:
- a well in the at least one raised structure, wherein the well is one of n-type and p-type;
- an anode of a type opposite the well and having a depth in the well of about 0.05 μm to about 3 μm;
- a cathode of a same type as the well and having a depth in the well of about 0.05 μm to about 3 μm;
- at least one contact electrically coupled to the anode;
- and
- at least one other contact electrically coupled to the cathode.
7 more elements
A semiconductor chip, comprising:
- a bulk semiconductor substrate;
- a plurality of raised semiconductor structures coupled to the substrate, at least one and less than all of the plurality of raised semiconductor structures having a width of about 5 nm to about 50 nm, wherein at least one and less than all of the plurality of raised structures is wider than a remainder of the plurality of raised structures;
- a plurality of electrostatic discharge (ESD) semiconductor devices situated within top portions of the wider raised semiconductor structures;
- and
- a plurality of at least one type of non-ESD semiconductor device situated at top portions of the remainder of the plurality of raised semiconductor structures.
2 more elements
Dependencies are inferred from the claim text.