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US 9,177,947 B2Granted
Semiconductor device having efficient capacitor arrangement
AssigneePS4 Luxco S.a.r.l.
InventorHiroyuki Fujimoto
Life of this patent
Estimating the term…
Abstract
The invention includes: multiple bit lines b1 to b5 arranged in parallel to each other at a first line pitch; multiple word lines w1 to w4 arranged in parallel to each other at a second line pitch greater than the first line pitch and intersecting with bit lines b1 to b5; and multiple capacitors. Respective center positions 4 of the multiple capacitors lie above the bit lines and are displaced by given distance C from the intersection of the bit line and the word line in a direction of arranging the word lines.
Claims20
A semiconductor device comprising:
- at least three first signal lines arranged sequentially in parallel with each other at a first line pitch;
- at least three second signal lines arranged in parallel with each other at a second line pitch and overlapping with the first signal lines as viewed in plan view;
- and
- a plurality of capacitors, each capacitor being arranged above an associated one of the first signal lines and being arranged over an associated one of the second signal lines, each capacitor of the plurality of capacitors being arranged with respect to a point where the associated one of the first signal lines overlaps with the associated one of the second signal lines when viewed in plan view,
- wherein each capacitor of the plurality of capacitors is displaced from the point where the associated one of the first signal lines overlaps with the associated one of the second signal lines when viewed in plan view, only in a direction parallel to a longitudinal direction of the first signal lines.
2 more elements
A semiconductor device comprising:
- at least three first signal lines having a first line, a second line, and a third line extended to a first direction and arranged sequentially in parallel with each other, the first and second lines being arranged at a first line pitch, and the second and third lines being arranged at the first line pitch;
- at least three second signal lines having a fourth line, a fifth line, and a sixth line extended to a second direction perpendicular to the first direction and arranged sequentially and in parallel with each other, the fourth and fifth lines being arranged at a second line pitch, and the fifth and sixth lines being arranged at the second line pitch and overlapping with the first signal lines as viewed in plan view;
- and
- at least seven storage elements each having a center associated with one of the first signal lines and one of the second signal lines,
- wherein a first storage element is associated with the first line and the fourth line, a second storage element is associated with the second line and the fourth line, a third storage element is associated with the third line and fourth line, a fourth storage element is associated with the first line and fifth line, a fifth storage element is associated with the second line and fifth line, a sixth storage element is associated with the third line and fifth line, and a seventh storage element is associated with the second line and sixth line,
- wherein the center of each of the first, the fifth and the sixth storage elements is arranged on a first straight line, the center of each of the third, fourth and the fifth storage elements is arranged on a second straight line, and the center of each of the second, the fifth, and the seventh storage elements is arranged on a third straight line, the storage elements arranged in a stacked arrangement whereby each of the storage elements is located above an associated one of the first signal lines and an associated one of the second signal lines, and
- wherein the center of each of the storage elements is displaced from a point where the associated one of the first signal lines overlaps with the associated one of the second signal lines when viewed in plan view, only in a direction parallel to a longitudinal direction of the first signal lines.
4 more elements
A semiconductor device having a stacked capacitor structure, comprising:
- at least three first signal lines having first to third lines arranged sequentially and each extending in a first direction, the first and second lines being arranged at a first line pitch, and the second and third lines being arranged at the first line pitch;
- a second signal line extending in a second direction perpendicular to the first direction to overlap with the first to third lines;
- a single first capacitor formed over an overlapping point of the first line and the second signal line;
- a single second capacitor formed over an overlapping point of the second line and the second signal line;
- and
- a single third capacitor formed over an overlapping point of the third line and the second signal line,
- wherein a center of the first capacitor and a center of the third capacitor are arranged on a first straight line,
- wherein a center of the second capacitor is arranged on a second straight line different from the first straight line and parallel with the first straight line,
- wherein each capacitor of the first, second and third capacitors is located above an associated one of the first signal lines and the second signal line, and
- wherein the center of each capacitor of the first, second and third capacitors is displaced from a point where the associated one of the first signal lines overlaps with the second signal lines when viewed in plan view, only in a direction parallel to a longitudinal direction of the first signal lines.
7 more elements
Dependencies are inferred from the claim text.