Advanced process control method for controlling width of spacer and dummy sidewall in semiconductor device

An APC method for controlling a width of a dummy sidewall in a semiconductor device, the method comprising:

• providing a semiconductor substrate;
• providing a target width of a gate;
• forming the gate on the semiconductor substrate, wherein the gate has a measured width;
• depositing a buffer layer covering the gate;
• depositing a dielectric layer covering the buffer layer, wherein the dielectric layer has a measured thickness;
• providing a target width of sum of the dummy sidewall and the buffer layer;
• determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of sum of the dummy sidewall and the buffer layer, and the measured thickness of the dielectric layer;
• and
• performing a trimming process on the dielectric layer for the determined trim time to form the dummy sidewall.