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US 9,177,872 B2Granted
Memory cells, semiconductor devices, systems including such cells, and methods of fabrication
AssigneeMicron Technology, Inc.
InventorGurtej S. Sandhu
Life of this patent
Estimating the term…
Abstract
A memory cell is disclosed. The memory cell includes a transistor and a capacitor. The transistor includes a source region, a drain region, and a channel region including an indium gallium zinc oxide (IGZO, which is also known in the art as GIZO) material. The capacitor is in operative communication with the transistor, and the capacitor includes a top capacitor electrode and a bottom capacitor electrode. Also disclosed is a semiconductor device including a dynamic random access memory (DRAM) array of DRAM cells. Also disclosed is a system including a memory array of DRAM cells and methods for forming the disclosed memory cells and arrays of cells.
Claims23
A memory cell comprising:
- a transistor comprising:
- a channel material comprising an indium gallium zinc oxide material extending above a substrate;
- and
- an insulative material on sidewalk of the channel material and extending a height of the channel material;
- and
- a capacitor in operative communication with the transistor, the capacitor comprising:
- a bottom capacitor electrode in direct physical contact with the channel material and extending laterally beyond the insulative material on the sidewalk of the channel material;
- and
- a capacitor dielectric material over the bottom capacitor electrode and having a lower surface coplanar with an upper surface of the channel material.
6 more elements
A method of forming a memory cell comprising:
- forming a transistor comprising:
- forming a first metal material supported by a substrate;
- forming a second metal material isolated from the first metal material by an insulative material;
- forming an opening in the insulative material and bordered at least in part by the first metal material and the second metal material, the opening defined by sidewalk of the insulative material;
- forming another insulative material on the sidewalls of the insulative material, the another insulative material defining another opening;
- and
- filling the another opening with a channel material at a temperature less than or equal to about 800 degrees Celsius, the channel material contacting the first metal material and extending above the substrate, the another insulative material disposed on sidewalls of the channel material and extending a height of the channel material, the channel material comprising an indium gallium zinc oxide material;
- and
- forming a capacitor in operative communication with the transistor, comprising:
- forming a third metal material physically abutting and contacting the channel material to form a bottom capacitor electrode extending laterally beyond the another insulative material on the sidewalls of the channel material;
- and
- forming a capacitor dielectric material over the third metal material, the capacitor dielectric material having a lower surface coplanar with an upper surface of the channel material.
9 more elements
A semiconductor device comprising:
- a dynamic random access memory (DRAM) array comprising:
- a plurality of DRAM cells, each DRAM cell of the plurality comprising:
- a transistor comprising:
- a channel material comprising an indium gallium zinc oxide material extending above a substrate;
- and
- an insulative material on sidewalls of the channel material and extending a height of the channel material;
- and
- a capacitor in operative communication with the transistor, the capacitor comprising:
- a bottom capacitor electrode in direct physical contact with the channel material and extending laterally beyond the insulative material on the sidewalk of the channel material;
- and
- a capacitor dielectric material over the bottom capacitor electrode and having a lower surface coplanar with an upper surface of the channel material.
8 more elements
A method of forming a memory array comprising:
- forming a plurality of memory cells, forming at least one memory cell of the plurality comprising:
- forming a first transistor comprising:
- forming a gate electrode isolated within an insulative material above a substrate;
- forming an opening in the insulative material to expose at least a portion of each of the substrate and the gate electrode;
- forming another insulative material within the opening, the another insulative material defining another opening;
- and filling the another opening with a channel material at a temperature less than or equal to about 800 degrees Celsius, the another insulative material on sidewalk of the channel material and extending a height of the channel material, the channel material comprising an indium gallium zinc oxide material;
- and
- forming a capacitor in electrical connection with the channel material, comprising:
- forming a bottom capacitor electrode physically abutting the channel material, the bottom capacitor electrode extending laterally beyond the another insulative material on the sidewalk of the channel material;
- and
- forming a capacitor dielectric material over the bottom capacitor electrode and having a lower surface coplanar with an upper surface of the channel material;
- and
- forming another memory cell of the plurality comprising:
- forming a second transistor above the capacitor;
- and
- forming a second capacitor above the second transistor.
13 more elements
A system comprising a memory array comprising a plurality of dynamic random access memory (DRAM) cells, each DRAM cell of the plurality comprising:
- a transistor comprising:
- a channel material comprising an indium gallium zinc oxide material extending above a substrate;
- and
- an insulative material on sidewalk of the channel material and extending a height of the channel material;
- and
- a capacitor in operative communication with the transistor, the capacitor comprising:
- a bottom capacitor electrode directly physically contacting the channel material and extending laterally beyond the insulative material on the sidewalk of the channel material;
- and
- a capacitor dielectric material over the bottom capacitor electrode and having a lower surface coplanar with an upper surface of the channel material.
6 more elements
Dependencies are inferred from the claim text.