US 9,177,871 B2 · Balancing asymmetric spacers

Abstract

An issue arises when manufacturing semiconductor circuits including PFETs with an SiGe alloy embedded in their source/drain regions and NFETs without any embedded SiGe alloy. In this case, the thickness of the NFET spacers is considerably greater than that of the PFET spacers. In order to alleviate this asymmetry in spacer thickness, a manufacturing flow is proposed wherein a spacer-reducing etching process is introduced before the salicidation. The etching process is performed directly after the ion implantation performed in order to form deep regions of source/drain regions of the NFETs. Thus, the spacer-reducing etching process may be performed in the presence of the same mask used during the NFET deep implantations. The spacer-reducing etching process results in thinning of the NFET spacer structures, thus alleviating the spacer thickness imbalance between NFETs and PFETs.

Claims21

Dependent claims

A method of forming an integrated circuit, comprising:

forming at least a first FET comprising a first gate structure and a first spacer structure formed on the sidewall of said first gate structure;
forming at least a second FET comprising a second gate structure and a second spacer structure formed on the sidewall of said second gate structure, a semiconductor alloy being embedded in the source and/or drain regions of said second FET;
forming a mask layer on said integrated circuit so as to cover said second FET and leave said first FET exposed;
performing an ion implantation in the presence of said mask layer;
and
after performing said ion implantation, performing an etching process in the presence of said mask layer so as to decrease the thickness of said first spacer structure.

3 more elements

Dependencies are inferred from the claim text.

Balancing asymmetric spacers

Life of this patent

Balancing asymmetric spacers

Life of this patent

Abstract

Claims21