Tungsten gates for non-planar transistors
AssigneeIntel Corporation
InventorsSameer S. Pradhan, Daniel B. Bergstrom, Jin-Sung Chun, Julia Chiu
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Abstract
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.
Claims25
A transistor gate, comprising:
- a pair of gate spacers;
- and
- a gate electrode disposed between the pair of gate spacers, wherein the gate electrode includes:
- an NMOS work-function material adjacent at least a portion of the pair of gates spacers and comprising aluminum, titanium, and carbon;
- a titanium-containing gate fill barrier adjacent the NMOS work-function material;
- and
- a tungsten-containing gate fill material adjacent the gate fill barrier.
A method of fabricating a transistor gate, comprising:
- forming a pair of gate spacers;
- and
- forming a gate electrode disposed between the pair of gate spacers comprising
- conformally depositing an NMOS work-function material adjacent the pair of gates spacers and comprising aluminum, titanium, and carbon;
- conformally depositing a titanium-containing gate fill barrier adjacent the NMOS work-function material;
- and
- depositing a tungsten-containing gate fill material adjacent the gate fill barrier.
A method of fabricating a non-planar transistor gate, comprising:
- forming a sacrificial non-planar transistor gate over a non-planar transistor fin;
- depositing a dielectric material layer over the sacrificial non-planar transistor gate and the non-planar transistor tin;
- forming non-planar transistor gate spacers from a portion of the dielectric material layer adjacent the sacrificial non-planar transistor gate;
- forming a source/drain region;
- removing the sacrificial non-planar transistor gate to form a gate trench between the non-planar transistor gate spacers and expose a portion of the non-planar transistor fin;
- forming a gate dielectric adjacent the non-planar transistor fin within the gate trench;
- forming a gate electrode disposed between the pair of gate spacers, comprising
- conformally depositing an NMOS work-function material adjacent the pair of gates spacers and comprising aluminum, titanium, and carbon;
- conformally depositing a titanium-containing gate fill barrier adjacent the NMOS work-function material;
- and
- depositing a tungsten-containing gate fill material adjacent the gate fill barrier;
- removing a portion of the gate electrode to form a recess between the non-planar transistor gate spacers;
- forming a capping dielectric structure within the recess;
- forming at least one dielectric material layer over the source/drain region, the non-planar transistor gate spacers, and the capping dielectric structure;
- and
- forming a contact opening through the at least one dielectric material to contact at least a portion of the source/drain region.
Dependencies are inferred from the claim text.