Methods for fabricating integrated circuits including barrier layers for interconnect structures
AssigneeGlobalfoundries Inc.
InventorsXunyuan Zhang, Tibor Bolom, Kun Ho Ahn, Bernd Hintze, Frank Koschinsky
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Abstract
Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.
Claims20
A method for fabricating an integrated circuit, the method comprising:
- forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process, wherein the barrier layer has a lower portion and a densified upper portion that has a greater density than the lower portion;
- depositing a liner-forming material overlying the barrier layer to form a liner;
- and
- depositing a conductive metal overlying the liner.
A method for fabricating an integrated circuit, the method comprising:
- etching a via-hole through an ILD layer of dielectric material to expose a metal line of a metallization layer above a semiconductor substrate;
- depositing a first tantalum nitride (TaN) layer into the via-hole overlying the metal line using an atomic layer deposition (ALD) process;
- depositing a second TaN layer into the via-hole overlying the first TaN layer using a physical vapor deposition (PVD) process to form a barrier layer that comprises the first and second TaN layers;
- forming a liner in the via-hole overlying the barrier layer;
- depositing a conductive metal seed layer into the via-hole overlying the liner;
- and
- filling a remaining portion of the via-hole with a conductive metal fill overlying the conductive metal seed layer.
A method for fabricating an integrated circuit, the method comprising:
- forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate, wherein forming the barrier layer comprises:
- depositing a first tantalum nitride (TaN) layer overlying the metal line using an atomic layer deposition (ALD) process;
- and
- densifying an upper portion of the first TaN layer by depositing a second TaN layer overlying the first TaN layer using a physical vapor deposition (PVD) process, wherein the barrier layer comprises the first and second TaN layers and has a lower portion and a densified upper portion that comprises the second TaN layer and the upper portion of the first TaN layer and that has a greater density than the lower portion;
- forming a liner overlying the barrier layer;
- and
- depositing a conductive metal overlying the liner.
Dependencies are inferred from the claim text.