External gettering method and device

#The disclosure relates generally to semiconductors, and more particularly, to semiconductor structures and corresponding methods of fabrication.

#Semiconductor devices are typically fabricated upon a wafer, which may be a silicon (Si)-based wafer, or other suitable materials known in the art. One process conventionally applied to Si wafers of semiconductor devices is known as a “stress relief” process. Stress relief processes are typically applied after the bulk substrate used to form the wafer has been thinned, for example, through a backside grinding process. At least in part due to the thinning process, areas of stress may be formed at the backside of the wafer.

#In the stress relief process, the thinned backside of the wafer is polished, thereby shifting some of the stress at the backside of the wafer away from the stress-relieved backside of the wafer and distributing it more evenly throughout the wafer. Examples of stress relief processes include dry polish (DP) techniques, such as mechano-chemical polishing (MCP) techniques, and chemical-mechanical polishing/planarization (CMP) techniques, as well as other techniques known in the art. The stress relief process increases the overall strength of the wafer, thereby increasing die strength, particularly for ultra thin dies (i.e., dies in the sub-50 μm range).

#FIG. 1 is a cross-sectional view of a semiconductor device with conventional intrinsic gettering;

#FIG. 2 is a cross-sectional view of a semiconductor device with conventional intrinsic gettering subject to grinding and/or thinning processes;

#FIGS. 3A-3B are cross-sectional views of a semiconductor device with conventional extrinsic gettering;

#In the following detailed description, reference is made to various embodiments of the invention. These embodiments are described with sufficient detail to enable those skilled in the art to practice them. It is to be understood that other embodiments may be employed, and that various structural, logical and electrical changes may be made. In addition, reference is made to various processes including multiple steps. It should be understood that these steps need not be performed in the order that they are listed, unless specifically stated as such.

#The term “substrate” used in the following description may include any supporting structure including, but not limited to, a semiconductor substrate that has an exposed substrate surface. A semiconductor substrate should be understood to include silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures, including those made of semiconductors other than silicon. The substrate, as well as devices formed therein, may be formed of any appropriate materials known in the art. When reference is made to a semiconductor substrate or wafer in the following description, previous process steps may have been utilized to form regions or junctions in or over the base semiconductor or foundation.

#In embodiments described below, external gettering is applied to semiconductor devices using electronic packaging. For example, in certain embodiments an external gettering element is applied to a backside of a semiconductor substrate. The external gettering element may be integrated with or arranged by electronic packaging that is typically used when fabricating a semiconductor device using the semiconductor substrate. For example, the external gettering element may be integrated with, or adhered by, an adhesive material that is applied to an already-polished backside of a substrate. In other embodiments described below, an encapsulation mold compound embedded with one or more additives may be formed around the semiconductor substrate.