Nonvolatile semiconductor memory device and method of manufacturing the same
AssigneeKabushiki Kaisha Toshiba
InventorsKiwamu Sakuma, Masahiro Kiyotoshi
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Abstract
According to one embodiment, a nonvolatile semiconductor memory device includes a stacked layer structure including first to n-th semiconductor layers (n is a natural number equal to or larger than 2) stacked in a first direction which is perpendicular to a surface of a semiconductor substrate, and an upper insulating layer stacked on the n-th semiconductor layer, the stacked layer structure extending in a second direction which is parallel to the surface of the semiconductor substrate, and first to n-th NAND strings provided on surfaces of the first to n-th semiconductor layers in a third direction which is perpendicular to the first and second directions respectively.
Claims22
A nonvolatile semiconductor memory device comprising:
- a structure including first to n-th semiconductor layers (n is a natural number equal to or larger than 2) stacked in a first direction, and an upper insulating layer stacked on the n-th semiconductor layer in the first direction, the structure extending in a second direction crossing to the first direction;
- and
- first to n-th NAND strings provided on surfaces of the first to n-th semiconductor layers in a third direction crossing to the first and second directions,
- wherein each of the first to n-th NAND strings includes memory cells connected in series,
- each of the memory cells includes a charge storage layer and a control gate electrode, and
- the upper insulating layer is not provided on the surface of the first to n-th semiconductor layers in the third direction and includes an oxide or a nitride of an element selected from a group of Al, Hf, Ta, Ti, and W.
A nonvolatile semiconductor memory device comprising:
- a structure including first to n-th semiconductor layers (n is a natural number equal to or larger than 2) stacked in a first direction, and an upper insulating layer stacked on the n-th semiconductor layer in the first direction, the structure extending in a second direction crossing to the first direction;
- and
- first to n-th memory cells provided on surfaces of the first to n-th semiconductor layers in a third direction crossing to the first and second directions,
- wherein each of the first to n-th memory cells includes a charge storage layer and a control gate electrode, and
- the upper insulating layer is not provided on the surfaces of the first to n-th semiconductor layers in the third direction and includes an oxide or a nitride of an element selected from a group of Al, Hf, Ta, Ti, and W.
Dependencies are inferred from the claim text.