US 9,177,805 B2 · Integrated circuits with metal-insulator-semiconductor (MIS) contact structures and methods for fabricating same

Abstract

Integrated circuits having metal-insulator-semiconductor (MIS) contact structures and methods for fabricating integrated circuits having metal-insulator-semiconductor (MIS) contact structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a fin structure formed from semiconductor material overlying a semiconductor substrate. The method includes depositing a layer of high-k dielectric material over the fin structure. Further, the method includes forming a metal layer or layers over the layer of high-k dielectric material to provide the fin structure with a metal-insulator-semiconductor (MIS) contact structure.

Claims20

Dependent claims

A method for fabricating an integrated circuit, the method comprising:

providing a fin structure formed from semiconductor material overlying a semiconductor substrate;
depositing a layer of high-k dielectric material over the fin structure;
forming a metal layer or layers over the layer of high-k dielectric material;
and
forming a metal-insulator-semiconductor (MIS) contact structure from the metal layer or layers, the layer of high-k dielectric material, and the fin structure.

2 more elements

A method for fabricating an integrated circuit, the method comprising:

providing a semiconductor substrate having a PFET source/drain region and an NFET source/drain region;
selectively forming a layer of high-k dielectric material over the PFET source/drain region;
and
depositing a metal layer or layers over the layer of high-k dielectric material over the PFET source/drain region and over the NFET source/drain region to form a metal-insulator-semiconductor (MIS) contact structure over the PFET source/drain region and a metal-semiconductor contact structure over the NFET source/drain region.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

14/166,660Filed 28 Jan 2014

Published

US 2015/0214059 A130 Jul 2015

Granted

3 Nov 2015

Term ends

Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 64/01314
Characterised by the conductor: the conductor comprising a layer of Ge, C or of compounds of Si, Ge or C contacting the insulator
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/6219
Fin field-effect transistors [FinFET]: characterised by the source or drain electrodes
H10D 64/01332
The insulator being formed after the semiconductor body, the semiconductor being silicon: making the insulator

Integrated circuits with metal-insulator-semiconductor (MIS) contact structures and methods for fabricating same

Life of this patent

Integrated circuits with metal-insulator-semiconductor (MIS) contact structures and methods for fabricating same

Life of this patent

Abstract

Claims20