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US 9,177,803 B2Granted
HK/MG process flows for P-type semiconductor devices
AssigneeGlobalfoundries Inc.
InventorsPeter Javorka, Juergen Faul, Ralf Richter, Jan Hoentschel
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Abstract
The present disclosure provides semiconductor device structures with a first PMOS active region and a second PMOS active region provided within a semiconductor substrate. A silicon germanium channel layer is only formed over the second PMOS active region. Gate electrodes are formed over the first and second PMOS active regions, wherein the gate electrode over the second PMOS active region is formed over the silicon germanium channel.
Claims5
A method of forming a semiconductor device structure, comprising:
- providing a first PMOS active region and a second PMOS active region in a semiconductor substrate;
- forming a first masking pattern over said first PMOS active region;
- forming a silicon germanium layer over said second PMOS active region in accordance with said first masking pattern;
- removing said first masking pattern;
- forming gate electrode structures over said first and second PMOS active regions;
- forming a second masking pattern over said first PMOS active region subsequently to said formation of gate electrode structures;
- performing a first implantation process in the presence of said second masking pattern with a first halo implant dose for forming halo regions in said second PMOS active region;
- removing said second masking pattern;
- forming a third masking pattern over said second PMOS active region;
- and
- performing a second implantation process in the presence of said third masking pattern with a second halo implant dose for forming lightly doped halo regions in said first PMOS active region, said second halo implant dose being substantially smaller than said first halo implant dose.
8 more elements
A method of forming a semiconductor device structure, comprising:
- providing a semiconductor substrate with a first PMOS active region and a second PMOS active region, of which only said second active region has a silicon germanium layer formed thereon;
- forming a first PMOS device on said first PMOS active region, said first PMOS device comprising a first gate electrode structure;
- forming a second PMOS device over said second PMOS active region, said second PMOS device comprising a second gate electrode structure formed on said silicon germanium layer;
- performing a first implantation process for forming halo regions in said second PMOS active region at opposing sides of said second gate electrode structure while said first PMOS active region is protected by a first masking pattern from being exposed to said first implantation process;
- and
- performing a second implantation process for forming halo regions in said first PMOS active region subsequent to said first implantation process while said second PMOS region is protected by a second masking pattern, wherein an implantation dose of said second implantation process is substantially smaller than an implantation dose of said first implantation process.
3 more elements
Dependencies are inferred from the claim text.