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US 9,177,668 B2Granted
Method and apparatus for bit cell repair
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSung-Chieh Lin, Jiann-Tseng Huang, Wei-Li Liao, Kuoyuan Hsu
Life of this patent
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Abstract
A method includes reading data from a subset of a plurality of memory bit cells of a non-volatile memory. The data identifies an address of at least one individual failed bit cell. The method further includes loading the data directly into a register, receiving an address of data to be accessed, determining if the received address is the address of any individual failed bit cell; and accessing the data of the register if the received address is the address of any individual failed bit cell.
Claims18
A method comprising:
- storing first data in a first subset of a plurality of memory bit cells of a non-volatile memory;
- reading the first data from the first subset to identify at least one individual failed bit cell;
- and
- storing second data in a second subset of the plurality of bit cells, the second data identifying an address of an individual failed bit cell among the at least one individual failed bit cells, the second subset being mutually exclusive from the first subset, wherein the second subset is in a same row or column of bit cells as a third subset of the plurality of bit cells, and the third subset is reserved for storage of payload data for repairing the at least one individual failed bit cell.
1 more element
A memory comprising:
- a plurality of memory bit cells arranged in rows and columns, the plurality of memory bit cells including:
- a first subset of bit cells configured to store data,
- a second subset of bit cells reserved for storage of address data identifying an address of at least one individual failed bit cell, and
- a third subset of bit cells reserved for storage of payload data for repairing the at least one individual failed bit cell.
1 more element
A method comprising:
- identifying at least one individual failed bit cell in a predetermined subset of a plurality of memory bit cells, wherein the plurality of bit cells are arranged in rows and columns;
- storing address data in a portion of a predetermined row or column of bit cells, the address data identifying an address of at least one of the individual failed bit cells, the predetermined row or column being separate from the predetermined subset of bit cells, the predetermined row or column including a payload bit cell reserved for repair of the at least one individual failed bit cells;
- and
- loading the contents of the predetermined row or column of bit cells into a register, said register being accessible each time an access to one of the individual failed bit cells is attempted.
1 more element
Dependencies are inferred from the claim text.