Method, memory controller and system for reading data stored in flash memory
AssigneeSilicon Motion, Inc.
InventorTsung-Chieh Yang
Life of this patent
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Abstract
An exemplary method for reading data stored in a flash memory. The method comprises: controlling the flash memory to perform a first read operation upon the memory cell with a first threshold voltage to obtain a first binary digit for representing a bit of the N bits data; performing an error correction hard decode according to the first binary digit; controlling the flash memory to perform a second read operation upon the memory cell with a second threshold voltage to obtain a second binary digit for representing the bit of the N bits data, if the error correction hard decode indicates an uncorrectable result; and performing an error correction soft decode according to the first binary digit and the second binary digit.
Claims17
A method for reading data stored in a flash memory, wherein the flash memory comprises a plurality of memory cells and stores N bit(s) data in a memory cell of the memory cells by programming the memory cell to one voltage state of 2N voltage states, the method comprises:
- controlling the flash memory to perform a first read operation upon the memory cell with a first threshold voltage to obtain a first binary digit for representing a bit of the N bits data;
- performing an error correction hard decode according to the first binary digit;
- controlling the flash memory to perform a second read operation upon the memory cell with a second threshold voltage to obtain a second binary digit for representing the bit of the N bits data, if the error correction hard decode indicates an uncorrectable result;
- performing an error correction soft decode according to the first binary digit and the second binary digit;
- and
- determining a threshold voltage shifting direction by obtaining a bit flopping phenomenon from comparing the first binary digit and the second binary digit when the error correction soft decode indicates a correctable result, wherein a bit flopping number showing bit-flopping phenomenon of all memory cells of a target page containing the memory cell is calculated, and the smaller the bit flopping number the more the threshold voltage shifting direction inclines to.
A memory controller for reading data stored in a flash memory, wherein the flash memory comprises a plurality of memory cells and stores N bit(s) data in a memory cell of the memory cells by programming the memory cell to one voltage state of 2N voltage states, the memory controller comprises:
- a control logic for controlling the flash memory to perform a first read operation upon the memory cell with a first threshold voltage to obtain a first binary digit for representing a bit of the N bits data;
- a decoder, coupled to the control logic, for performing an error correction hard decode according to the first binary digit;
- and
- a threshold voltage tracking unit,
- wherein the control logic is further for controlling the flash memory to perform a second read operation upon the memory cell with a second threshold voltage to obtain a second binary digit for representing the bit of the N bits data, if the error correction hard decode indicates an uncorrectable result, and the decoder is further for performing an error correction soft decode according to the first binary digit and the second binary digit, and the threshold voltage tracking unit determines a threshold voltage shifting direction by obtaining a bit flopping phenomenon from comparing the first binary digit and the second binary digit when the error correction soft decode indicates a correctable result, wherein a bit flopping number showing bit-flopping phenomenon of all memory cells of a target page containing the memory cell is calculated, and the smaller the bit flopping number the more the threshold voltage shifting direction inclines to.
A memory system for reading data stored in a flash memory, wherein the flash memory comprises a plurality of memory cells and stores N bit(s) data in a memory cell of the memory cells by programming the memory cell to one voltage state of 2N voltage states, the memory system comprises:
- a control logic for controlling the flash memory to perform a first read operation upon the memory cell with a first threshold voltage to obtain a first binary digit for representing a bit of the N bits data;
- a decoder, coupled to the control logic, for performing an error correction hard decode according to the first binary digit;
- and
- a threshold voltage tracking unit,
- wherein the control logic is further for controlling the flash memory to perform a second read operation upon the memory cell with a second threshold voltage to obtain a second binary digit for representing the bit of the N bits data, if the error correction hard decode indicates an uncorrectable result, and the decoder is further for performing an error correction soft decode according to the first binary digit and the second binary digit, and the threshold voltage tracking unit determines a threshold voltage shifting direction by obtaining a bit flopping phenomenon from comparing the first binary digit and the second binary digit when the error correction soft decode indicates a correctable result, wherein a bit flopping number showing bit-flopping phenomenon of all memory cells of a target page containing the memory cell is calculated, and the smaller the bit flopping number the more the threshold voltage shifting direction inclines to.
Dependencies are inferred from the claim text.