1T1b and 2T2b flash-based, data-oriented EEPROM design

A method for operating an one-transistor-one-bit (1T1b) Flash-based EEPROM cell array during a byte erase operation, the method comprising:

• providing a 1T1b Flash-based EEPROM cell array comprising:
• an 1T1b Flash-based EEPROM cell array divided into a plurality of pages, each page being laid in a row having a number of bytes in X direction, each byte including eight bits, each bit being associated with a memory cell having a triple P-well (TPW) node, a word line WL node connected to a common WL for each page in the X direction, a bit line BL node configured to connect a global BL in Y direction perpendicular to the X direction, and a source line SL node configured to connect a global SL in the Y direction, wherein the plurality of pages is arranged in the number of columns of bytes in the Y direction, each column of bytes sharing a common TPW node connected to all TPW nodes of all memory cells in the column;
• a decoder circuit connected to each common WL in the X direction associated with each of the plurality of pages;
• a low-voltage PGM buffer circuit made from PMOS and NMOS devices with power supply voltages of 3V or less and connected to all the global BLs in the Y direction respectively through a plurality of BL-select transistors;
• and
• a source line control block circuit configured to connect all the global SLs in the Y direction respectively through a plurality of SL-select transistors;
• biasing the 1T1b Flash-based EEPROM cell array for erasing a selected byte in a selected page by
• applying a negative voltage level through the decode circuit to a selected WL associated with the selected byte belonging to the selected page, the negative voltage level being approximately −5 V;
• applying a +5 V level through the decoder circuit to all unselected WLs;
• coupling 0 V from the low-voltage PGM buffer circuit to gates of the plurality of BL-select transistors to close all global BLs for preventing leakage;
• applying approximately +10 V level to a selected TPW node associated with the selected byte;
• applying approximately 0 V level to all un-selected TPW nodes;
• coupling 10 V or less to all selected global BLs/SLs associated with the selected byte through corresponding PN junctions between the selected TPW node and the selected global BLs/SLs;
• and
• setting all un-selected global BLs/SLs to 0V or float state;
• wherein a bias difference between the selected WL and the selected BLs is about 16 V for inducing FN tunneling effect for erasing the selected byte.

A method for operating a one-transistor-one-bit (1T1b) Flash-based EEPROM cell array during a page program operation, the method comprising:

• providing a 1T1b Flash-based EEPROM cell array comprising:
• a 1T1b Flash-based EEPROM cell array divided into a plurality of pages, each page being laid in a row having a number of bytes in X direction, each byte including eight bits, each bit being associated a memory cell with a triple P-well (TPW) node, a word line WL node connected to a common WL for each page in the X direction, a bit line BL node configured to connect a global BL in Y direction perpendicular to the X direction, and a source line SL node configured to connect a global SL in the Y direction, wherein the plurality of pages is arranged in the number of columns of bytes in the Y direction, each column of bytes sharing a common TPW node connected to all TPW nodes of all memory cells in the column;
• a decoder circuit connected to each common WL in the X direction associated with each of the plurality of pages;
• a low-voltage PGM buffer circuit made from PMOS and NMOS devices with power supply voltages of 3V or less and connected to all the global BLs in the Y direction respectively through a plurality of BL-select transistors;
• and
• a source line control block circuit configured to connect all the global SLs in the Y direction through a plurality of SL-select transistors;
• biasing the 1T1b Flash-based EEPROM cell array for pre-charging all global SLs by
• applying a moderate positive voltage level between 0 V and 5V to all WLs from the decoder circuit;
• setting the TPW nodes to ground reference voltage level at 0 V;
• applying a high gate voltage level of approximately 16 V to gates of all SL-select transistors to allow passage of 10V pre-charge voltage from a bottom common bus to the global SLs;
• applying a LV Vdd level of 3V or less to gates and drain nodes of the plurality of BL-select transistors to set them in non-conduction state for prevent leakages;
• biasing the 1T1b Flash-based EEPROM cell array for programming a selected bit in the selected page with pre-charged SLs by
• ramping only the moderate positive voltage level to the selected WL associated with the selected page to a high program voltage level of approximately 16 V, and keeping the moderate positive voltage level for other WLs;
• keeping the TPW nodes in the ground reference voltage level;
• applying a low gate voltage level of 0 V to turn off the SL-select transistor connecting to the SL of the selected bit, and keeping other SL-select transistors On to allow passage of the common bus voltage of 10 V to un-selected global SLs;
• applying the LV Vdd level to gates of all BL-select transistors and applying a PGM inhibit voltage level to all but one drain nodes of the BL-select transistors to inhibit discharging of the corresponding global BLs except applying a PGM voltage level to said one drain node of the BL-select transistor to allow discharge of the BL associated with the selected bit;
• wherein the PGM inhibit voltage level is equal to the LV Vdd of 3 V or less and the PGM voltage level is 0 V.

A method for operating an one-transistor-one-bit (1T1b) Flash-based EEPROM cell array during a read operation, the method comprising:

• providing a 1T1b Flash-based EEPROM cell array comprising:
• an 1T1b Flash-based EEPROM cell array divided into a plurality of pages, each page being laid in a row having a number of bytes in X direction, each byte including eight bits, each bit being associated with a memory cell having a triple P-well (TPW) node, a word line WL node connected to a common WL for each page in the X direction, a bit line BL node configured to connect a global BL in Y direction perpendicular to the X direction, and a source line SL node configured to connect a global SL in the Y direction, wherein the plurality of pages is arranged in the number of columns of bytes in the Y direction, each column of bytes sharing a common TPW node connected to all TPW nodes of all memory cells in the column;
• a decoder circuit connected to each common WL in the X direction associated with each of the plurality of pages;
• a low-voltage PGM buffer circuit made from PMOS and NMOS devices with power supply voltages of 3V or less and connected to all the global BLs in the Y direction respectively through a plurality of BL-select transistors;
• and
• a source line control block circuit configured to connect all the global SLs in the Y direction respectively through a plurality of SL-select transistors;
• biasing the 1T1b Flash-based EEPROM cell array for reading a selected byte by
• applying a low read voltage level of approximately 2.5 V through the decode circuit to a selected WL associated with the selected byte;
• applying a ground reference voltage level of 0 V to other unselected WLs;
• setting the TPW node associated with the selected byte to the ground reference voltage level;
• applying 1 V or less from the Low-voltage PGM buffer circuit through a sense amplifier to all selected global BLs corresponding to the selected byte;
• letting the un-selected global BLs to float;
• and
• applying the ground reference voltage level from the source line control block circuit to all global SLs.