Pulse control for nonvolatile memory

A nonvolatile memory device in which programming or erasing of data are each to be performed using multiple program-verify cycles, the nonvolatile memory device comprising:

• a wordline;
• a channel;
• a memory cell between the wordline and the channel to store the data;
• a driver to selectively couple one of the wordline or the channel to one voltage reference;
• and
• a pulsing mechanism to control an electrical connection between the other of the wordline or the channel to another voltage reference, in a manner to apply discrete voltage pulses across the memory cell;
• where the pulsing mechanism is to apply the discrete voltage pulses across the memory cell repeatedly during the program portion of each of the multiple program-verify cycles;
• where the pulsing mechanism and other voltage reference are to apply a rest period between pulses applied during the program portion of each of the multiple program-verify cycles, each pulse having a duration of no greater than approximately 100 nanoseconds.

In a nonvolatile device in which programming or erasing of data are each to be performed using multiple program-verify cycles, the nonvolatile memory device having a wordline, a channel, a memory cell between the wordline and the channel to store the data, an improvement comprising:

• providing a driver to selectively couple one of the wordline or the channel to one voltage reference and providing a pulsing mechanism to control an electrical connection between the other of the wordline or the channel to another voltage reference, in a manner to apply discrete voltage pulses across the memory cell;
• providing a register to store at least two of:
• (a) pulse frequency, (b) duty cycle and (c) number of pulses, the nonvolatile memory device to apply the discrete pulses using the pulsing mechanism during the program portion of each of the multiple program-verify cycles, the discrete pulses to be applied in dependence upon the at least two, the register being dynamically programmable by a remote memory controller;
• where the pulsing mechanism and other voltage reference are to apply a rest period between the discrete pulses applied during the program portion of each of the multiple program-verify cycles, each pulse having a duration of no greater than approximately 50 nanoseconds, and where the rest period is at least 500 nanoseconds.