Memory device with multiple cell write for a single input-output in a single write cycle
AssigneeIntegrated Silicon Solutions Inc.
InventorsMingShiang Wang, Kyoung Chon Jin
Life of this patent
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Abstract
A non-volatile memory device incorporates a write buffer within a multi-level column decoder to enable multiple memory cells associated with a single write driver to be written in parallel. In this manner, in a non-volatile memory such as a flash memory that performs batch write operation, a group of data bits for a single I/O can be written to the memory cells at a time, thereby reducing the number of write cycles required for writing a block of program data and increasing the speed of write operation.
Claims17
A non-volatile memory device, comprising:
- a two-dimensional array of non-volatile memory cells, each memory cell being accessed by a word line and a bit line, a first portion of the array of memory cells being associated with a first write driver and the first write driver being associated with a first input-output of the non-volatile memory device;
- a row decoder configured to control a plurality of word lines corresponding to rows of the array of memory cells, the row decoder being configured to activate one of the plurality of word lines in response to a row address;
- a first multi-level column decoder configured to control a plurality of bit lines corresponding to columns of the first portion of the array of memory cells, the first multi-level column decoder being configured to activate two or more bit lines within the first portion of the array of memory cells simultaneously in response to a plurality of column addresses;
- and
- a plurality of write buffers coupled to intermediate nodes of the first multi-level column decoder, the intermediate nodes of the first multi-level column decoder being nodes between a first decoding level and a second decoding level of the first multi-level column decoder,
- wherein the plurality of write buffers store program data for memory cells associated with the first write driver at a first power supply voltage level and the plurality of write buffers provides the stored program data to two or more bit lines to be written to memory cells associated with the first write driver at a second power supply voltage level greater than the first power supply voltage level, the first multi-level column decoder activating the two or more bit lines within the first portion of the array of memory cells simultaneously to write the program data provided by the write buffers into respective memory cells associated with the activated word line, the program data being written to two or more memory cells in the first portion of the array associated with the first input-output of the non-volatile memory device.
A method of writing program data to a non-volatile memory device, the non-volatile memory device comprising a two-dimensional array of non-volatile memory cells, each memory cell being accessed by a word line and a bit line, a first portion of the array of memory cells being associated with a first write driver and the first write driver being associated with a first input-output of the non-volatile memory device, the method comprising:
- initiating a write operation at the non-volatile memory device;
- receiving an input address and a block of program data;
- decoding a row address of the input address to activate a word line;
- decoding a column address of the input address using two or more levels of decoding;
- storing, using a first voltage level, a set of program data for the first portion of the array of memory cells and associated with the first write driver, the set of program data being associated with memory cell addresses having common most significant address bits of the column address;
- activating two or more bit lines within the first portion of the array of memory cells and associated with the first write driver simultaneously in response to the common most significant bits column address;
- applying a second voltage level greater than the first voltage level to the stored program data;
- and
- programming the program data into a set of memory cells within the first portion of the array of memory cells associated with the activated bit lines and the activated word line, the program data being written to two or more memory cells in the first portion of the array associated with the first input-output of the non-volatile memory device.
Dependencies are inferred from the claim text.