Flash memory circuit
AssigneeShanghai Huahong Grace Semiconductor Manufacturing Corporation
InventorJing Gu
Life of this patent
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Abstract
A memory circuit is provided, including: a plurality of sectors, where each sector includes at least two parallel rows of memory units; a first control line, a second control line and a word line corresponding to each row of memory units, where at least two of the first control lines which are in the same sector and neighboring with each other are connected, and at least two of the second control lines which are in the same sector and neighboring with each other are connected; and a plurality of bit lines perpendicular with the word lines. The number of the first and second control lines may be reduced, so decoding units which control the control lines may occupy less chip areas, thereby reducing chip areas occupied by the memory circuit.
Claims11
A memory circuit, comprising:
- a plurality of sectors, where each sector comprises at least two parallel rows of memory units, and each memory unit comprises a first bit unit and a second bit unit;
- a first control line, a second control line and a word line corresponding to each row of memory units, where the first control line controls the first bit units, the second control line controls the second bit units, and the word line is parallel with the first and second control lines, and where at least two neighboring first control lines which are in the same sector are connected, and at least two neighboring second control lines which are in the same sector are connected;
- and
- a plurality of bit lines perpendicular with the word lines,
- wherein the memory unit comprises a semiconductor substrate and a gate on the semiconductor substrate, the first bit unit and the second bit unit are on two sides of the gate, and the gate is coupled with the word line which is adapted for selecting the memory unit;
- wherein the memory unit further comprises a source in the semiconductor substrate which is on a side of the first bit unit far away from the gate, and a drain in the semiconductor substrate which is on a side of the second bit unit far away from the gate, where the source is coupled with a first bit line on one side of the memory unit, and the drain is coupled with a second bit line on another side of the memory unit;
- and
- wherein when a programming process is performed to one of the memory units, a word line programming voltage, a first control line programming voltage and a second control line programming voltage, which are higher than a threshold voltage of the memory unit, are respectively applied to the word line, the first control line and the second control line of the memory unit;
- and a first bit line programming voltage and a second bit line programming voltage having different values are respectively applied to the first bit line and the second bit line on two sides of the memory unit.
Dependencies are inferred from the claim text.