3D non-volatile memory device having wordlines with large width
AssigneeSK hynix Inc.
InventorJin-Su Park
Life of this patent
Estimating the term…
Abstract
A nonvolatile memory device includes first to N-th memory blocks, wherein N is an integer and N≧3. Each memory block, of the first to N-th memory blocks comprises first to (M−1)-th strings, wherein each string, of the first to (M−1)-th strings, includes drain-side memory cells, source-side memory cells, and a pipe transistor connecting the drain-side memory cells and the source-side memory cells, where M is an integer and M≧2, and an M-th string, including drain-side memory cells formed adjacent to the first string, of a first to (M−1)-th strings, and including source-side memory cells formed adjacent to an (M−1)-th string of the first to (M−1)-th strings.
Claims12
A nonvolatile memory device comprising first to N-th memory blocks, wherein N is an integer and N≧3, and
- wherein each memory block, of the first to N-th memory blocks, comprises:
- first to (M−1)-th strings, wherein each string, of the first to (M−1)-th strings, includes drain-side memory cells, source-side memory cells, and a pipe transistor connecting the drain-side memory cells and the source-side memory cells, where M is an integer and M≧2;
- and
- an M-th string, including drain-side memory cells formed adjacent to the first string, of a first to (M−1)-th strings, and including source-side memory cells formed adjacent to an (M−1)-th string of the first to (M−1)-th strings
- wherein each of the first to N-th memory blocks corresponds to the unit of erase operation.
A nonvolatile memory device comprising a plurality of memory blocks, wherein each memory block, of the plurality memory blocks, comprises:
- a first plurality of drain-side memory cells arranged in a first drain-side string and a first plurality of source-side memory cells arranged in a first source-side string, wherein the first drain-side string and the first source-side string are connected by a first pipe transistor;
- a second plurality of drain side memory cells arranged in a second drain-side string and a second plurality of source-side memory cells arranged in a second source-side string, wherein
- the second drain-side string is connected to a second source-side string of an adjacent memory block, of the plurality of memory block, via a second pipe transistor, and
- the second source-side string is connected to a second drain-side string, of a different adjacent memory block, of the plurality of memory blocks, via a third pipe transistor,
- wherein the each of memory blocks corresponds to the unit of erase operation.
Dependencies are inferred from the claim text.