10T NVSRAM cell and cell operations

A 10T NVSRAM memory cell circuit with a DRAM-like charge-sensing scheme, the 10T NVSRAM memory cell comprising:

• a SRAM cell comprising two inverters cross-coupled to a first pass transistor and a second pass transistor commonly gated by a first word line and respectively coupled drains to a first bit line and a second bit line and sources to a first data node and a second data node, the first data node and the second data node respectively being outputted from the two invertors, each inverter including a PMOS device connected to a first power line and a NMOS device connected to a second power line, the first power line and the second power line being operated between a VDD power supply and ground and being separated from a common Nwell node;
• and
• a Flash cell comprising a first cell string and a second cell string sharing a common P-sub, the first/second cell string including a first/second Select transistor and a first/second Flash transistor connected in series, the first and the second Select transistors being gated commonly by a select-gate control line and respectively associated with a first drain terminal coupled to the first data node and a second drain terminal coupled to the second data node, the first and the second Flash transistors being gated commonly by a second word line and respectively associated with a first source terminal and a second source terminal, the first source terminal and the second source terminal being floating;
• wherein the second word line is configured to ramp up to a voltage above the VDD level sufficient to couple two different charge levels respectively from the first Flash transistor and the second Flash transistor to the first data node and the second data node, the SRAM cell uses the two cross-coupled inverters to amplify the two different charge levels to one at the VDD level and another one at VSS in a two-step operation;
• wherein the first Flash transistor and the second Flash transistor are configured to flexibly increase their channel lengths to make a difference of the two different charge levels coupled to the first data node and the second data node to be substantially larger than any unmatched parasitic capacitance between the first data node and the second data node.