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US 9,177,641 B2Granted
Memory device
OwnerMasahiro Takahashi, Tsuneo Inaba +2inventors
InventorsMasahiro Takahashi, Tsuneo Inaba, Dong Keun Kim, Ji Wang Lee
Life of this patent
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Abstract
According to one embodiment, a memory device includes a memory cell, a sense amplifier, and a resistor. The sense amplifier includes a first input and a second input, outputs a signal in accordance with a difference between the first and second inputs, and is selectively coupled at a second input to the memory cell. The resistor is in a first path between the first input of the sense amplifier and a ground node.
Claims11
A memory device comprising:
- a memory cell comprising a variable resistance;
- a sense amplifier comprising a first input and a second input, the sense amplifier outputting a signal in accordance with a difference between the first and second inputs, and being selectively coupled at the second input to the memory cell;
- a resistor in a first path between the first input of the sense amplifier and a ground node;
- and
- a second path comprising the memory cell between the second input of the sense amplifier and the ground node,
- wherein the resistor has a value between a first resistance of the second path including the memory cell holding first data and a second resistance of the second path including the memory cell holding second data, and
- wherein the resistor comprises one of a gate resistance, a diffusion layer resistor, a metal resistor, a transistor resistor, and a combination thereof.
4 more elements
A memory device comprising:
- a memory cell with a variable resistance;
- a sense amplifier comprising a first input and a second input, the sense amplifier outputting a signal in accordance with a difference between the first and second inputs, and being selectively coupled at a second input to the memory cell;
- a first transistor coupled at a first end to the first input of the sense amplifier and clamping a potential of a second end thereof;
- a resistor between the second end of the first transistor and a ground node;
- and
- a second transistor coupled at a first end thereof to the second input of the sense amplifier and clamping a potential of a second end thereof,
- wherein the resistor has a value between a resistance of a path between the second end of the second transistor and the ground node including the memory cell holding first data and a resistance of a path between the second end of the second transistor and the ground node including the memory cell holding second data, and
- wherein the resistor comprises one of a gate resistance, a diffusion layer resistor, a metal resistor, a transistor resistor, and a combination thereof.
5 more elements
Dependencies are inferred from the claim text.