Wide voltage range high performance sense amplifier
AssigneeSTMicroelectronics International N.V.
InventorsAnuj Grover, Gangaikondan Subramani Visweswaran
Life of this patent
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Abstract
A dual rail SRAM array includes a plurality of columns of memory cells each coupled between two bit lines. A sense amplifier is coupled between each pair of bit lines. Capacitors are positioned between the sense amplifier outputs and the bit lines, thereby separating the sense amplifier from the bit lines. The memory cells are powered with an array supply voltage. The sense amplifier is powered with a peripheral supply voltage. During a read operation of the memory array, the bit lines are precharged to the array supply voltage. The sense amplifier is precharged to the peripheral supply voltage or to an intermediate voltage.
Claims19
A device, comprising:
- a memory cell coupled between a high voltage supply and a low voltage supply;
- a first bit line coupled to the memory cell;
- a second bit line;
- a sense amplifier coupled to the first and the second bit line, the sense amplifier having a first output and a second output;
- a first capacitor coupled directly between the first output and the first bit line;
- and
- a second capacitor coupled directly between the second output and the second bit line.
A device, comprising:
- address circuitry powered by a first high supply voltage;
- an array of memory cells coupled to the address circuitry and powered by a second high supply voltage, the array including:
- a plurality of columns of memory cells;
- a plurality of pairs of bit lines, each pair of bit lines being coupled to a respective column of memory cells;
- a plurality of sense amplifiers each coupled to a respective column of memory cells and a respective pair of bit lines and each including:
- a first output and a second output;
- a first capacitor having a first electrode coupled to the first output and a second electrode coupled to a first bit line of the pair of bit lines;
- and
- a second capacitor having a first electrode coupled to the second output and a second electrode coupled to a second bit line of the respective pair of bit lines;
- a data read circuit configured to read data from the array of memory cells.
A method for reading data from a memory cell, the method comprising:
- precharging a bit line to a first high supply voltage;
- coupling the memory cell to the bit line by supplying an enable signal to a word line coupled to the memory cell, the memory cell being powered by the first high supply voltage and a low supply voltage;
- precharging an output of a sense amplifier to a precharge voltage;
- and
- amplifying a voltage difference between the bitline and a reference voltage by supplying an enable signal to the sense amplifier, a capacitor being coupled between the output and the bit line.
Dependencies are inferred from the claim text.