8T based SRAM cell and related method

A method comprising:

• performing a read function with the eight transistor SRAM device comprising:
• coupling an eight transistor static random-access memory (SRAM) device having a first inverter and a second inverter, wherein the first inverter and the second inverter include a reverse bit line controlled feedback N-MOSFET (NMOS) transistor coupled with a P-MOSFET (PMOS) pull-up transistor and an NMOS pull-down transistor, with a first signal line to form a communication path, wherein the first signal line is in communication with the reverse bit line controlled feedback NMOS transistor of the second inverter and a first access transistor;
• coupling the eight transistor SRAM device with a second signal line to form a communication path, wherein the second signal line is in communication with the reverse bit line controlled feedback NMOS transistor of the first inverter and a second access transistor;
• and
• coupling each of the first access transistor and the second access transistor with a third signal line to form a communication path;
• and
• isolating a node in the SRAM device using the reverse bit line controlled feedback NMOS transistor in the first inverter and the second inverter.

A method comprising:

• performing a write function with the eight transistor SRAM device comprising:
• coupling an eight transistor static random-access memory (SRAM) device having a first inverter and a second inverter, wherein the first inverter and the second inverter include a reverse bit line controlled feedback N-MOSFET (NMOS) transistor coupled with a P-MOSFET (PMOS) pull-up transistor and an NMOS pull-down transistor, with a first signal line to form a communication path, wherein the first signal line is in communication with the reverse bit line controlled feedback NMOS transistor of the second inverter and a first access transistor;
• coupling the eight transistor SRAM device with a second signal line to form a communication path, wherein the second signal line is in communication with the reverse bit line controlled feedback NMOS transistor of the first inverter and a second access transistor;
• and
• coupling each of the first access transistor and the second access transistor with a third signal line to form a communication path;
• and
• controlling feedback between the first inverter and the second inverter by activating the reverse bit line controlled feedback transistors of the first inverter and the second inverter, in response to performing the write function.