Back to results
US 9,177,634 B1Granted
Two gate pitch FPGA memory cell
AssigneeXilinx, Inc.
InventorsSteven P. Young, Yang Song, Nui Chong
Life of this patent
Estimating the term…
Abstract
A memory cell includes a first inverter and a second inverter, wherein the first inverter and second inverter are cross-coupled using a storage node and an inverse storage node; a data node and an inverse data node, wherein the data node and inverse data node are next to a first side of the memory cell; and an address line controlling access to the storage node and the inverse storage node by the data and inverse data nodes; wherein the memory cell comprises a two gate pitch memory cell.
Claims16
A memory cell comprising:
- a first inverter and a second inverter, wherein the first inverter and second inverter are cross-coupled using a storage node and an inverse storage node;
- a first poly track, wherein a gate of the first inverter and a gate of the second inverter are implemented on the first poly track;
- a data node and an inverse data node, wherein the data node and inverse data node are next to a first side of the memory cell;
- and
- an address line controlling access to the storage node and the inverse storage node by the data and inverse data nodes;
- wherein the memory cell comprises a two gate pitch memory cell.
3 more elements
An integrated circuit, comprising:
- a plurality of memory cells having at least four memory cells arranged in a first row;
- a data line connecting the at least four memory cells;
- wherein one of the at least four memory cells comprises:
- a first inverter and a second inverter, wherein the first inverter and second inverter are cross-coupled using a storage node and an inverse storage node;
- a data node and an inverse data node, wherein the data node and inverse data node are next to a first side of the one of the memory cells;
- and
- an address line controlling access to the storage node and the inverse storage node by the data and inverse data nodes;
- wherein the one of the at least four memory cells comprises a two gate pitch memory cell;
- and
- wherein the data node and the inverse data node of the one of the at least four memory cells are shared with another one of the at least four memory cells that is next to the one of the at least four memory cells.
7 more elements
Dependencies are inferred from the claim text.