Bit line write assist for static random access memory architectures

A Static Random Access Memory (SRAM) device, comprising:

• a memory cell array;
• a pair of complimentary bit lines traversing the memory cell array for writing data to memory cells of the memory cell array, wherein each of the bit lines has a first end and a second end;
• a pair of complimentary write drivers proximate to the first end of the bit lines, wherein a first of the write drivers is configured to write to a first of the bit lines, wherein a second of the write drivers is configured to write to a second of the bit lines;
• and
• a write assist circuit proximate to the second end of the bit lines that is configured to receive a pre-charge signal to assist the write drivers in transitioning the bit lines from a logical zero state to a logical one state;
• the write assist circuit further configured to receive a boost signal to assist the write drivers in transitioning the bit lines from a logical one state to a logical zero state;
• wherein the write assist circuit comprises:
• a pair of cross-coupled transistors, wherein a first of the transistors has a drain terminal coupled to the first bit line, wherein a second of the transistors has a drain terminal coupled to the second bit line;
• a pull-up circuit configured to couple the drain terminal of the first transistor and the drain terminal of the second transistor to a logical one reference voltage in response to receiving the pre-charge signal;
• and
• a pull-down circuit configured to couple the source terminal of the first transistor and the source terminal of the second transistor to a logical zero reference voltage in response to receiving the boost signal.