Method and apparatus for calibrating write timing in a memory system

A method of operation in a controller IC, the method comprising:

• transmitting a clock signal and a strobe signal to a dynamic random access memory (DRAM), the strobe signal to convey phase information to the DRAM for sampling data associated with the strobe signal;
• aligning at the DRAM, arrival of the strobe signal with arrival of the clock signal such that the strobe signal arrives at the DRAM based on an edge transition of the clock signal;
• performing a read leveling operation to establish a timing offset to apply to a data sampler, the data sampler to sample data received from the DRAM in connection with a read operation;
• and
• after performing the read leveling operation, calibrating a clock cycle delay between commands received at the DRAM and data corresponding to the commands, wherein calibrating the clock cycle delay comprises adjusting the strobe signal by an integer number of cycles, responsive to whether a first data pattern, written to a location in the DRAM, matches a second data pattern retrieved from the location in the DRAM, the second pattern received by the data sampler using the timing offset.

An integrated circuit (IC) device to control the operation of a dynamic random access memory (DRAM), the IC device comprising:

• circuits to transmit a clock signal and a strobe signal to the DRAM, the strobe signal to convey phase information to the DRAM for sampling data associated with the strobe signal;
• calibration logic to perform an operation to establish a receiver phase offset for receiving read data, and, the calibration logic to align at the DRAM, arrival of the strobe signal with arrival of the clock signal using a delayed strobe signal;
• and
• wherein the calibration logic is to selectively adjust transmit timing of the strobe signal by an integer number of cycles, responsive to whether a first data pattern, written to a location in the DRAM using the delayed strobe signal, matches a second data pattern retrieved from the location in the DRAM, the second pattern received by the data sampler using the receiver phase offset.

A method of operation in a controller IC, the method comprising:

• step for transmitting a clock signal and a strobe signal to a dynamic random access memory (DRAM), the strobe signal to convey phase information to the DRAM for sampling data associated with the strobe signal;
• step for aligning at the DRAM, arrival of the strobe signal with arrival of the clock signal such that the strobe signal arrives at the DRAM based on an edge transition of the clock signal;
• step for performing a read leveling operation to establish a timing offset to apply to a data sampler, the data sampler to sample data received from the DRAM in connection with a read operation;
• and
• after performing the read leveling operation, step for calibrating a clock cycle delay between commands received at the DRAM and data corresponding to the commands, wherein the step for calibrating the clock cycle delay comprises adjusting the strobe signal by an integer number of cycles, responsive to whether a first data pattern, written to a location in the DRAM, matches a second data pattern retrieved from the location in the DRAM, the second pattern received by the data sampler using the timing offset.