Semiconductor device with low voltage programming/erasing operations

A semiconductor device comprising:

• a first memory array including a first word line, a first reference word line, a first local bit line crossing the first word line and the first reference word line, a first memory cell provided at an intersection of the first word line and the first local bit line, and a first reference cell provided at an intersection of the first reference word line and the first local bit line;
• a second memory array including a second word line, a second reference word line, a second local bit line crossing the second word line and the second reference word line, a second memory cell provided at an intersection of the second word line and the second local bit line, and a second reference cell provided at an intersection of the second reference word line and the second local bit line;
• a third memory array including a third word line, a third reference word line, a third local bit line crossing the third word line and the third reference word line, a third memory cell provided at an intersection of the third word line and the third local bit line, and a third reference cell provided at an intersection of the third reference word line and the third local bit line;
• a fourth memory array including a fourth word line, a fourth reference word line, a fourth local bit line crossing the fourth word line and the fourth reference word line, a fourth memory cell provided at an intersection of the fourth word line and the fourth local bit line, and a fourth reference cell provided at an intersection of the fourth reference word line and the fourth local bit line;
• a fifth memory array including a fifth word line, a fifth local bit line crossing the fifth word line, and a fifth memory cell provided at an intersection of the fifth word line and the fifth local bit line;
• a first global bit line connected to the first local bit line and the fifth local bit line;
• a sixth memory array including a sixth word line, a sixth local bit line crossing the sixth word line, and a sixth memory cell provided at an intersection of the sixth word line and the sixth local bit line;
• a second global bit line connected to the second local bit line and the sixth local bit line;
• a first sense amplifier having a first input to which the first memory array is connected and a second input to which the second memory array is connected, and amplifies a difference in potentials of the first input and the second input;
• a second sense amplifier having a third input to which the third memory array is connected and a fourth input to which the fourth memory array is connected, and amplifies a difference in potentials of the third input and the fourth input;
• a first switch connected between the first input and the third input;
• and
• a second switch connected between the second input and the fourth input,
• wherein the first reference cell and the third reference cell store information different to each other,
• wherein the second reference cell and the fourth reference sell store information different to each other,
• wherein the first input is connected to the first and fifth memory arrays though the first global bit line,
• wherein the second input is connected to the second and sixth memory arrays through the second global bit line,
• wherein, when reading information from the first and third memory cells, the second and fourth reference cells are selected, and the second switch short-circuits the second input and the fourth input, and
• wherein, when reading information from the second and fourth memory cells, the first and third reference cells are selected, and the first switch short-circuits the first input and the third input.