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US 9,177,626 B2Granted
Semiconductor memory device
OwnerNaoki Shimizuinventor
Life of this patent
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Abstract
A semiconductor memory device includes: banks each including a memory cell array; word lines connected to rows of each of the banks; an address latch circuit configured to latch a full address for specifying one of the word lines, the full address including a first address and a second address; and a control circuit configured to ignore a reset operation for the first address as a target of a set operation, and overwrite the first address in accordance with the set operation when receiving a first command for specifying a reset operation for a bank and a set operation for the first address.
Claims14
A semiconductor memory device comprising:
- banks each including a memory cell array;
- word lines connected to rows of each of the banks;
- an address latch circuit which latches a full address for specifying one of the word lines, the full address including a first address and a second address;
- and
- a control circuit which ignores a reset operation for the first address as a target of a set operation, and overwrites the first address in accordance with the set operation when receiving a first command for specifying a reset operation for a bank and a set operation for the first address.
2 more elements
Dependencies are inferred from the claim text.