Memory interface offset signaling
AssigneeQUALCOMM Incorporated
InventorsShree Krishna Pandey, Dexter T. Chun
Life of this patent
Estimating the term…
Abstract
A memory interface includes circuitry configured for applying a variable delay to a portion of a data signal and applying a variable delay to a data strobe. The delayed data strobe samples the delayed portion of the data signal. Delayed portions of the data signal are spaced away from non-delayed portions of the data signal by alternating the routing of delayed bits and non-delayed bits of the data signal. A training block determines and sets a value of the variable delay corresponding to a largest value of a number of recorded eye aperture widths.
Claims17
A memory interface method, comprising:
- applying an operating delay to only a first set of bits of a data channel of a memory interface waveform;
- transmitting the delayed first set of bits across a memory interface;
- transmitting a second set of bits of the data channel across the memory interface, in which a first set of signal lines transferring the first set of bits is interwoven with a second set of signal lines transferring the second set of bits on the data channel;
- applying a strobe delay to a first strobe to generate a second strobe;
- transmitting the first strobe and the second strobe across the memory interface;
- sampling the delayed first set of bits with the second strobe;
- and
- sampling the second set of bits with the first strobe.
A memory interface, comprising:
- means for applying an operating delay to only a first set of bits of a data channel of a memory interface waveform;
- means for transmitting the delayed first set of bits across the memory interface;
- means for transmitting a second set of bits of the data channel across the memory interface, in which a first set of signal lines transferring the first set of bits is interwoven with a second set of signal lines transferring the second set of bits on the data channel;
- means for applying a strobe delay to a first strobe to generate a second strobe;
- means for transmitting the first strobe and the second strobe across the memory interface;
- means for sampling the delayed first set of bits with the second strobe;
- and
- means for sampling the second set of bits with the first strobe.
A memory interface, comprising:
- a first data path coupled to a first set of bits of a data signal;
- a first variable delay circuit coupled between the first data path and a first latch;
- a second data path coupled between a second set of bits of the data signal and a second latch, in which the first data path is at least partially interwoven with the second data path;
- a first strobe path coupled to a first strobe signal;
- a second variable delay circuit coupled between the first strobe path and the first latch;
- and
- a second strobe path coupled between the first strobe signal and the second latch.
Dependencies are inferred from the claim text.